WO2011081232A1

WO2011081232A1 - Computing system and method for selectively implementing process persistence using nvram and volatile ram

Info

Publication number: WO2011081232A1
Application number: PCT/KR2009/007920
Authority: WO
Inventors: 김효진
Original assignee: 주식회사 프롬나이
Priority date: 2009-12-29
Filing date: 2009-12-29
Publication date: 2011-07-07

Abstract

Disclosed is a computing system. The computing system may include a processor performing a computing operation for a plurality of processes, a storage class memory (SCM) operating as at least part of a main memory, and a volatile memory operating as another part of the main memory together with the SCM.

Description

Computing system and method for selectively implementing process persistence using NVRAM and volatile RAM

It relates to a computing system and a computing method, and more particularly to a computing system and a method that selectively implements process persistence for a plurality of processes.

Non-volatile random access memory (hereinafter referred to as NVRAM) is a RAM that does not lose data even when the power supply is cut off.

NVRAM includes a battery backed RAM that is maintained in a non-volatile state by a battery, and a storage class memory that maintains stored data without a power supply due to device characteristics without a power supply.

Storage Class Memory (hereinafter referred to as SCM) is a form of Non-Volatile Random Access Memory (NVRAM), in which memory cells are self-volatile and rapidly Byte address access is possible.

SCMs currently commercialized or expected to be commercialized include PCRAM (Phase change RAM), MRAM (Magnetroresistive RAM), FeRAM (Ferroelectric RAM), and the like. In particular, FeRAM was released and commercialized by Ramtron, and PCRAM, which has high integration strengths, was nearing commercialization by companies such as Intel and Samsung.

On the other hand, this SCM has been researched to be utilized as a storage device, a disk cache, etc. in the system hierarchy.

A computing system and computing method are provided that implement the persistence of some individual processes being selected without changing the source code of the individual processes.

In addition, a computing system and computing method are provided in which the persistence of some selected processes and some information for operating the system is maintained even if an unexpected interruption of power supply occurs during execution of the process.

According to one aspect of the invention, a processor that performs computing operations for a plurality of processes, NVRAM operating as at least part of main memory, volatile memory operating as another part of the main memory together with the NVRAM, and the NVRAM and the A computing system is provided that includes a memory controller for controlling at least one of volatile memories.

According to an embodiment of the present invention, the NVRAM may be a storage class memory (SCM). Hereinafter, the case of SCM will be described as an example, but embodiments of other forms of NVRAM, such as a battery backed RAM, are not excluded by this exemplary description.

Wherein the SCM serves as a main memory in a computing operation associated with at least some of the processes selected as persistent processes, and the volatile memory is another portion of the plurality of processes not selected as a persistent process. It may serve as a main memory in computing operations associated with the process of.

According to an embodiment of the present invention, when a new first process is executed in addition to the plurality of processes, if there is a process associated with the first process among the plurality of processes, the first process inherits persistence from the associated process. I can receive it.

The computing system may further include a temporary power supply unit supplying power to the process and the SCM for a threshold time when the power supply of the computing system is cut off.

In this case, when the power supply of the computing system is cut off, at least some of the registers, cache data, and device state information of the processor are stored in the SCM within the threshold time.

In this case, at least some of the registers, cache data, and device state information of the processor may be stored at a first predetermined address in the SCM.

And when the power supply of the computing system is resumed after the power supply is cut off, at least one of a register, the cache data, and the device state information of the processor is restored from a preset first address in the SCM. .

According to an embodiment of the present invention, the SCM is at least one of a phase change RAM (PCRAM), a magnetroresistive RAM (MRAM), and a ferroelectric RAM (FeRAM).

The memory controller stores a slab cache and a file page generated in a computing operation of the plurality of processes in the SCM.

The memory controller may allocate a paging space for the DRAM during the booting of the computing system and manage the DRAM through an array of zone descriptors and page descriptors.

In addition, when the computing system is turned on or turned off, the memory controller generates a slab cache (Slab) generated in a computing operation process for a portion of the recovery processes not selected as the permanent process. Cache) and file pages can be deleted from the SCM.

According to another aspect of the present invention, by using a storage class memory (SCM) as a main memory, performing a computing operation associated with at least some of the processes selected as a persistent process among a plurality of processes, and using volatile memory as the main memory Thus, performing a computing operation associated with some other process not selected as a persistent process of the plurality of processes is provided.

By dynamically or flexibly specifying the persistence of a process, a persistent computing environment tailored to the user can be implemented.

Storage overhead or operating time overhead to implement process persistence can be minimized.

In addition, the system does not need to be frozen to maintain process continuity, allowing execution to continue while ensuring system stability or consistency.

1 illustrates a computing system in accordance with one embodiment of the present invention.

2 is a conceptual diagram illustrating a processing method of a persistent process in a computing system according to an exemplary embodiment of the present invention.

3 is a conceptual diagram illustrating a processing method of a non-persistent process in a computing system according to an exemplary embodiment of the present invention.

4 illustrates a physical memory map that recognizes SCMs and DRAMs within a computing system in accordance with one embodiment of the present invention.

5 illustrates a computing method in accordance with one embodiment of the present invention.

FIG. 6 illustrates a process of determining whether a new process is a permanent process when a new process is executed in the computing method according to an embodiment of the present invention.

FIG. 7 illustrates a processing method when the power of the computing system is cut off in the computing method according to an exemplary embodiment of the present invention.

8 illustrates a processing method when power is resumed to a computing system, in accordance with an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the embodiments. Like reference numerals in the drawings denote like elements.

1 illustrates a computing system 100 in accordance with one embodiment of the present invention.

The computing system 100 includes a processor 110, a main memory 120, a memory controller 130, and a storage 140 that process a plurality of processes.

According to an embodiment of the present invention, the main memory 120 is a storage class memory (SCM) 121 that operates as a main memory in a computing operation for at least some of the plurality of processes, and another part of the plurality of processes. Dynamic Random Access Memory (DRAM) 122 that acts as the main memory in the computing operation for. Here, the DRAM 122 is an example of volatile memory capable of operating as a main memory, and may be replaced with another type. In addition, as described above, the SCM is only one form of NVRAM, and examples of NVRAM other than the SCM are not excluded from the present invention. Same as below.

The main memory 120 reads and temporarily stores a required file from the storage 140 for computing operations for a plurality of processes processed by the processor 110, and may be used to cause the computing operation of the process to be terminated. The data during the computing operation for the process and the result data are stored until the data is transferred to the storage 140.

In conventional computing systems where only volatile memory, such as DRAM, is the main memory for computing operations, data loss due to sudden power off has been a problem.

As a solution to such data loss, studies based on check pointing have been conducted. Check pointing is a technique for periodically storing an execution image of a process in main memory in storage.

However, this check pointing technique has low efficiency due to large space overhead and execution time overhead. In addition, such check pointing schemes do not back up data continuously, so there is an interval between data backup points, and thus data changed between data backup points may be lost.

Also, in order to maintain data consistency during the data backup operation by the check pointing technique, freezing occurs because the process cannot be processed.

Therefore, in order to prevent data loss even in the event of sudden power failure, an attempt to adopt main memory as non-volatile memory, such as non-volatile RAM (NVRAM), is required.

However, rather than configuring the entire main memory only with nonvolatile memory, using nonvolatile memory and volatile memory together can take advantage of both memory characteristics and make up for the shortcomings. Improvement in terms of reliability and availability can be achieved.

According to one embodiment of the invention, a plurality of processes performed in the computing system are divided into a persistent process and a non-persistent process.

A persistent process is herein where all data and state generated during the execution of the computing operation for the process are preserved even when the computing system is powered off, so that the execution of the computing operation when the system is powered on again. This is a lasting process.

A non-persistent process, on the other hand, is a process in which data and state generated during the execution of a computing operation for a process are not preserved by powering off the computing system.

The main memory 120 of the computing system 100 according to an embodiment of the present invention is the main memory in the computing operation for the non-persistent process and the SCM 121 operating as the main memory in the computing operation for the persistent process. DRAM 122 that operates.

As described above, the SCM 121 includes, for example, a phase change RAM (PCRAM), a magnetroresistive RAM (MRAM), a ferroelectric RAM (FeRAM), and the like. However, this is merely exemplary, and the present invention is not limited by some embodiments.

In addition, the SCM 121 and the DRAM 122 may be controlled by the memory controller 130.

Of the plurality of processes processed in the computing system 100, at least some of the processes set by the user and / or selected by the system operating system are selected as persistent processes.

Here, whether or not a specific process is selected as a persistent process is called setting the persistence of the process.

This setting of persistence may be subject to other criteria, depending on the user of the computing system. For example, in the computing system of a graphic designer, an image editing process may be set as a permanent process, and in the author's computing system, a word processor may be set as a permanent process.

Such setting criteria of persistence and / or specific persistence setting values for individual processes may be changed dynamically at any point in time. For example, some processes may be temporarily or persistently set by the user or by the system during operation of the computing system.

Meanwhile, when a new process is executed, the persistence of the new process may be set by a user or a system. Here, the setting of the persistence by the system is that the persistence of the new process is set by the setting criteria of the persistence established in the computing system in advance.

In this case, either of the process's persistence setting by the user and the process's persistence setting by the system may be designated as having a high priority. For example, when a new process is executed in the computing system 100, the computing system 100 may receive an answer from the user as to whether to set the new process as a permanent process. And, the answer received in this way can take precedence over the result of setting the persistence by other criteria established by the system itself.

As described above, a setup program may be included in the computing system 100 to allow a user to set persistence for an individual process.

Meanwhile, according to an embodiment of the present invention, when the newly executed process is associated with another process, it is also possible to inherit the persistence of the associated process.

For example, when the newly executed process is an associated application of another process or a dependent process, if the process is a persistent process, the newly executed process is determined as a persistent process.

Of course, in the case of a process such as a shell of the operating system, since most of the other processes are associated with, the kernel process and the shell of the operating system are set to be a persistent process unconditionally, so that such persistence is not inherited by other related processes. It is also possible to set exceptions.

Thus, according to embodiments of the present invention, a plurality of processes are selectively selected as a persistent process or a non-persistent process, and in each case, the SCM 121 or the DRAM 122 operate as the main memory.

The process by which the persistent or non-persistent process is processed by the computing system 100 will be described in more detail below with reference to FIG. 2.

2 is a conceptual diagram 200 illustrating a method of processing a persistent process in the computing system 100 according to an embodiment of the present invention.

According to an embodiment of the present invention, the computing system 100 may simultaneously recognize the SCM 121 and the DRAM 122 as main memory. In this case, caching or paging may be performed in the SCM 121 for the persistent process and for the DRAM 122 for the non-persistent process, respectively, in the same manner as in the conventional main memory.

In this embodiment, since both the SCM 121 and the DRAM 122 are recognized and operated by the computing system 100 and the memory controller 130, the SCM 121 and the DRAM 122 are in parallel, and / Or complementarily. Thus, there is no difference in layer or priority on the system between the SCM 121 and the DRAM 122.

In some cases, however, due to hardware limitations or for some other reason, either the SCM 121 or the DRAM 122 is selected to function as a high priority primary memory and the other is a separate auxiliary. It may be chosen to function as a memory.

Hereinafter, according to some embodiments of the present invention, an embodiment in which either the SCM 121 or the DRAM 122 is selected to function as a high priority primary memory and the other is selected to function as a separate auxiliary memory. However, the present invention should not be limitedly interpreted by this form. In particular, as described above, an embodiment in which both the SCM 121 and the DRAM 122 are recognized and operated by the computing system 100 and the memory controller 130 should not be excluded.

Again, an embodiment in which either the SCM 121 or the DRAM 122 is selected to function as a high priority primary memory and the other is selected to function as a separate auxiliary memory will be described.

According to the present embodiment, the SCM 121 may be recognized by the kernel 210 as a basic memory of the computing system 100. In this case, the SCM 121 is accessed through the memory controller 130 and the interface accessed by the kernel 210.

In order to minimize modifications to the conventional kernel and to improve driving efficiency, the slab cache 230 of the kernel 210, the persistent processes 220, and the non-persistent processes may be independent of the process persistence. Are all stored in the basic memory SCM 121.

In the case of the file page 250, the kernel 210, the persistent processes 220, and all of the non-persistent processes may be stored in the SCM 121, which is a basic memory.

In the case of anonymous page 240, only those of persistent processes 220 are stored in SCM 121.

The SCM manager manages the above contents, and the contents of the data stored in the SCM cell 270 are the same as those of the normal main memory.

3 is a conceptual diagram 310 for explaining a method of processing a non-persistent process in the computing system 100 according to an embodiment of the present invention.

As described above, in the embodiment in which the computing system 100 can simultaneously recognize the SCM 121 and the DRAM 122 as main memory, the SCM 121 and the DRAM 122 are each a permanent process and a non-persistent process. It acts as a separate main memory for the process.

However, in the embodiment described above with reference to FIG. 2, since the DRAM 122 is an auxiliary memory, the structure of the memory control unit 130 that recognizes the basic memory is changed to recognize the DRAM 122, thereby changing the DRAM 122. The computing system 100 may be provided with a separate manager and an interface for recognizing or driving the DRAM 122.

In this case, the slab cache 230 and the file mapped pages 250 of the non-persistent processes 310 are stored in the SCM 121, as described in the conceptual diagram of FIG. 2.

On the other hand, dirty pages whose contents have been changed after being loaded into memory for the file page may be stored in the SCM, and clean pages having no contents may be stored in the DRAM.

And, an anonymous page 320 of non-persistent processes is stored in DRAM 122. However, since the DRAM 122 is an embodiment of the secondary memory of the SCM 121 which is the primary memory, the process of the DRAM manager 330 performing the paging to the DRAM cell 340 may be different from that of the conventional main memory. Can be.

In some embodiments of the present invention, the memory controller 130 manages the SCM 121 and the DRAM 122 through a kernel in which some code is modified based on the Linux kernel 2.6.21.

However, the present invention should not be construed as being limited to being implemented by some operating system kernel environments, such as the Linux kernel, and the Linux kernel 2.6.21-based implementation is merely an embodiment.

Hereinafter, an implementation based on Linux kernel 2.6.21 will be described, and description of the implementation by another embodiment will be omitted.

In this embodiment, the kernel 210 recognizes the DRAM 121 with ioremap () during the booting process and performs paging for a space starting with a virtual address received as the return value.

In this embodiment, the additionally and auxiliaryly recognized DRAM 122 is managed by an array of zone descriptors called vrzoone and page descriptors called vrzone_mem_map_t. Since the vrzone or vrzone_mem_map_t data structure itself is initialized during the boot process, it may exist on the SCM 121.

Meanwhile, in the embodiment described with reference to FIGS. 2 and 3, the SCM 121 stores a slab cache, a file page, and the like of a non-persistent process, and these are stored when the computing system 100 is powered off and on. Can be removed. That is, residuals such as metadata of a non-persistent process may be erased.

Of course, the residue erasing process of this non-persistent process may be set to a point in time when the computing system is powered off, or a point in time when the power is turned back on, or any other specific point in time.

4 illustrates an example physical memory map 400 that recognizes the SCM 121 and the DRAM 122 within a computing system in accordance with one embodiment of the present invention.

In this embodiment, an address translation method for the DRAM 122 is provided so that the kernel 210 can access the DRAM 122.

In the kernel, various values such as a physical address, a virtual address, a page table entry (PTE), a page descriptor address, and a physical page frame number (PFN) may be converted to and used for memory access.

And even when the kernel approaches DRAM 122, these values are converted to each other and used. The macros / functions corresponding to the basic address translation method are indicated with the prefix "vr_".

For example, page_addess () used when converting a physical address into a virtual number of weeks is set to correspond to vr_page_address ().

However, the conversion between the PTE and the PFN does not require a separate additional conversion method for the DRAM 122.

A DRAM manager (330 of FIG. 3) for managing DRAM may utilize Linux's Buddy system code. Although in this embodiment, DRAM 122 is used only for anonymous page 320 of non-persistent processes 310. However, this is only one embodiment for the implementation of the present invention, and in a computing system that simultaneously recognizes and implements the SCM 121 and the DRAM 122, a slab cache for non-persistent processes 310 may be used. As described above, the DRAM 122 may also be used for the 230 and the file pages 250.

Meanwhile, interfaces for allocating and freeing DRAM pages are also displayed with names prefixed with "vr_". For example, the alloc_pages () function corresponds to vr_alloc_pages (). DRAM pages are used in anonymous pages of non-persistent processes, and vr_do_wp_page (), vr_do_no_page (), and vr_do_anonymous_page () functions are added to the page fault routine to allocate when a request for an anonymous page 320 occurs.

If any process is handled by the processor, it is identified in step S510 whether the process is a persistent process.

However, as described above, when the persistence of the process is not specified in advance, the persistence may be determined by receiving a user input through a user interface so as to be designated by the user.

In addition, for a newly started process, if there is an associated process, it is possible to inherit the persistence of the associated process.

Policies on inheritance of persistence can be established in various ways, for example, a child process (or dependent process) of a non-persistent process can be determined as a non-persistent process.

Among persistent processes, processes that have been assigned persistence by kernel processes and users can inherit persistence from child processes.

However, as described above, some of the persistent processes do not inherit persistence to child processes. For example, a shell created during the boot of a computing system becomes the parent process of all processes, so inheriting persistence from a child process makes all processes processed in the computing system persistent. It is specified not to inherit persistence.

On the other hand, the persistence of such a process may be stored and managed in a persistence field in a data structure. In these fields a non-persistent process, for example, can have its identity set to zero, a process that is persistent and inherits persistence to child processes 1, which is persistent but 2 that does not inherit persistence to child processes. Each identification value can be set.

In this case, as described above, when the persistence of the processor is designated or released in the middle, the process of changing the value of the persistence field is performed.

When the persistence is designated for the non-persistent process, the pages allocated to the DRAM 122 are transferred to the SCM 121, and when the process is successfully completed, the value of the persistence field is changed from 0 to 1.

Specifically, the pages allocated to the DRAM 122 are found through the list of the vm_area_struct data structure, which is a region describer of the process, and the contents of the pages of the DRAM 122 are assigned to the pages newly allocated in the SCM 121. Copy and modify the PTE for it. In this process, if the persistence specification process fails due to lack of memory or the like, the pages are restored to the DRAM 122, and a report on the failure of the persistent assignment is returned.

The process of releasing persistence for a process that has been designated as a persistent process is contrary to the above.

Referring back to FIG. 5, the computing method is thus identified in step S510 whether it is a persistent process for any process, and if it is a persistent process, then in step S520 the SCM 121 is stored in main memory. In operation S540, the process is performed by selecting the DRAM 122 as the main memory in operation S530.

When a new process is executed in step S610, it is determined in step S620 whether the persistence for the new process has already been specified, that is, whether the persistence specification already exists. If the persistence is already specified, step S510 of FIG. 5 or less is performed.

However, if the persistence is not specified in advance, it is determined in step S630 whether there is a process associated with the newly executed process. If there is an associated process, in step S640 the persistence of the associated processor is inherited and step S510 of FIG. 5 or less is performed again.

Otherwise, if it is determined in step S630 that there is no associated processor, after receiving the persistent designation input through the user interface (S650), the following steps (S510) of FIG. 5 are performed.

Details are as described above with reference to FIGS. 2 to 5.

While the processes are being performed in the computing system 100, when a shutdown of the system power is detected (S710), power is supplied from the temporary power supply (not shown) included in the computing system 100 for a threshold time.

Then, in step S720, necessary information for system restart, such as a register of the processor, cache data, and device information of the computing system, is backed up to the SCM 121 within the threshold time.

Here, the temporary power supply unit is not limited to a specific physical device, but may be in any form such as a battery, an uninterruptible power supply system (UPS), a dual power supply line, and the like, which can be simply inserted into the system.

In addition, the threshold time may be differently designated by a setting, but may be typically specified at several milliseconds to several tens of milliseconds.

This backup ensures that all data about the persistent process and the data needed to restart the system are not lost, even in the event of a sudden power off at any point in time.

In some embodiments, an application may be forcibly reset by a user when an error occurs in the computing system, and then the system may be restored to the state before the error.

On the other hand, in the backup process of step 720, it is also possible to back up to any address in the SCM 121, according to an embodiment of the present invention, a space for such a backup in advance, such as power off, When an event is detected, it is also possible to always back up the specified location.

FIG. 8 illustrates a processing method when power supply to the computing system is resumed after the power supply shutdown event of FIG. 7 according to an embodiment of the present invention.

When the power supply to the computing system is resumed, in step S810, data such as processor registers, cache data, and device information, which have been backed up in step S720 of FIG. 7, may be restored.

As described above, if a dedicated space for a backup is designated in the SCM 121 in the backup process of step S720, data may be recovered by directly accessing an address of the dedicated space in this recovery process.

After restarting the system, the process of step S510 or less continues.

As described above, although the present invention has been described with reference to limited embodiments and drawings, the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

Claims

A processor that performs computing operations for the plurality of processes;

NVRAM operating as at least part of main memory;

A volatile memory operating with the NVRAM as another part of the main memory; And

A memory controller controlling at least one of the NVRAM and the volatile memory

Including, a computing system.
The method of claim 1,

And the NVRAM is a storage class memory (SCM).
The method of claim 2,

The SCM serves as a main memory in computing operations associated with at least some processes selected as persistent processes among the plurality of processes,

And the volatile memory serves as a main memory in computing operations associated with some other process of the plurality of processes that is not selected as a persistent process.
The method of claim 2,

When a new first process runs

And if there is a process associated with the first process among the plurality of processes, the first process inherits persistence from the associated process.
The method of claim 2,

When the power supply of the computing system is cut off, further comprising a temporary power supply for supplying power to the process and the SCM for a threshold time,

And when power to the computing system is interrupted, at least some of the registers, cache data, and device state information of the processor are stored in the SCM within the threshold time.
The method of claim 5,

And when the power supply of the computing system is cut off, at least some of the registers, cache data, and device state information of the processor are stored at a predetermined first address in the SCM.
The method of claim 6,

And when power to the computing system is resumed, at least one of a register, the cache data, and the device state information of the processor is restored from a first predetermined address in the SCM.
The method of claim 2,

The SCM is at least one of a phase change RAM (PCRAM), a magnetroresistive RAM (MRAM), a ferroelectric RAM (FeRAM).
The method of claim 2,

The memory controller is configured to store a slab cache and a file page generated in a computing operation for the plurality of processes in the SCM.
The method of claim 9,

The memory controller allocates a paging space for the DRAM during the booting of the computing system and manages the DRAM through an array of zone descriptors and page descriptors.
The method of claim 9,

When the computing system is turned on or turned off, the memory controller generates a slab cache generated in a computing operation process for a part of the processes not selected as the persistent process among the plurality of processes and stored in the SCM and DRAM. Cache) and page related data from the SCM.
Utilizing storage class memory (SCM) as main memory to perform a computing operation associated with at least some processes selected as persistent processes among a plurality of processes; And

Utilizing volatile memory as main memory to perform computing operations associated with some other processes not selected as persistent processes among the plurality of processes

Including, computing method.
The method of claim 12,

When a new first process is executed in addition to the plurality of processes, determining the persistence of the first process based on whether a process associated with the first process among the plurality of processors is selected as the permanent process

Further comprising a computing method.
The method of claim 12,

When the power supply of the computing system is cut off, power is supplied from a temporary power supply for a threshold time, and at least some of the registers, cache data, and device state information of the processor are stored in the SCM.

Further comprising a computing method.
The method of claim 14,

At least some of the processor's registers, cache data, and device state information are stored at a predetermined first address in the SCM.
The method of claim 15,

Restoring at least one of a register, the cache data, and the device state information of the processor from a preset first address in the SCM when the power supply of the computing system is resumed.

Computing method further comprising.
A computer-readable recording medium having recorded thereon a program for performing the method of any one of claims 12 to 16.