WO2012011751A2 - Master clock transmitting apparatus using a shared transmission line - Google Patents

Master clock transmitting apparatus using a shared transmission line Download PDF

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Publication number
WO2012011751A2
WO2012011751A2 PCT/KR2011/005374 KR2011005374W WO2012011751A2 WO 2012011751 A2 WO2012011751 A2 WO 2012011751A2 KR 2011005374 W KR2011005374 W KR 2011005374W WO 2012011751 A2 WO2012011751 A2 WO 2012011751A2
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signal
master clock
transmission line
mclk
vdd
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PCT/KR2011/005374
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French (fr)
Korean (ko)
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WO2012011751A3 (en
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김종필
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(주)실리콘화일
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Definitions

  • the present invention relates to a master clock transmission apparatus, and more particularly, to a power signal sharing transmission line for transmitting a power signal VDD and the master clock signal MCLK together between a neighboring first system and a second system.
  • the present invention relates to a master clock transmission apparatus using a shared transmission line that does not require a separate master clock transmission line.
  • a system generally uses a clock source in the system to receive a master clock for the operation of the system or receives a clock from another system.
  • a device that generates a clock is called a master device, and a device that receives a clock is called a slave device, and they have a predominant relationship with each other.
  • connection lines In addition, in the case of a normal system, it is not a problem if there is no problem in adding a connection line, but it is very important to reduce the number of connection lines when two systems must be connected to a minimum line.
  • FIG. 1 illustrates a transmission apparatus for transmitting a master clock between systems in the related art.
  • a conventional inter-system master clock transmission apparatus 100 includes a first system 110, a second system 130, a power signal transmission line 121, a ground signal transmission line 123, and a master clock. And a transmission line 125.
  • the first system 110 and the second system 130 transmit and receive the power signal VDD through the power signal transmission line 121 and the ground signal VDD through the ground signal transmission line 123, respectively. do.
  • the first system 110 receives the master clock signal MCLK transmitted by the second system 130 through the master clock transmission line 125.
  • the conventional inter-system master clock transmission apparatus 100 uses a separate master clock transmission line 125 in addition to the power signal transmission line 121 and the ground signal transmission line 123, thereby making the two systems the minimum line.
  • the circuit becomes complicated as the number of connecting lines increases, leading to unnecessary power loss.
  • the technical problem to be solved by the present invention is to provide a separate master by having a power signal sharing transmission line for transmitting the power signal (VDD) and the master clock signal (MCLK) together between the neighboring first system and the second system
  • the present invention provides a master clock transmission apparatus using a shared transmission line that does not require a clock transmission line.
  • a master clock transmission device for transmitting and receiving comprising: a first system (210) receiving the master clock signal (MCLK) and the transmission signal; A second system 230 for transmitting the master clock signal MCLK and the transmission signal; A ground signal transmission line 223 for transmitting and receiving a ground signal VSS between the first system 210 and the second system 230; And a power signal sharing transmission line 221 for transmitting a power signal VDD and the master clock signal MCLK together.
  • the present invention does not require a separate master clock transmission line by including a power signal sharing transmission line for transmitting the power signal VDD and the master clock signal MCLK together between neighboring first and second systems.
  • FIG. 1 illustrates a transmission apparatus for transmitting a master clock between systems in the related art.
  • FIG. 2 illustrates a transmitter for briefly explaining a concept of transmitting a master clock between systems of the present invention.
  • FIG. 3 illustrates a transmission apparatus for describing in detail a method of transmitting a master clock between systems of the present invention.
  • FIG. 4 is a timing diagram of a power signal and a masker clock when transmitting a master clock between systems according to the present invention.
  • FIG. 2 illustrates a transmitter for briefly explaining a concept of transmitting a master clock between systems of the present invention.
  • the inter-system master clock transmission apparatus 200 of the present invention may include a first system 210, a second system 230, a power signal sharing transmission line 221, and a ground signal transmission line 223. Include.
  • the first system 210 loads a predetermined transmission signal, that is, a power signal VDD, a master clock signal MCLK, and a ground signal VSS, to the second system 230.
  • a predetermined transmission signal that is, a power signal VDD, a master clock signal MCLK, and a ground signal VSS.
  • the master clock signal MCLK is transmitted through a separate master clock transmission line 125 and instead of the power signal sharing VDD and the power supply signal VDD and the master clock signal MCLK.
  • the master clock signal MCLK is transmitted through a separate master clock transmission line 125 and instead of the power signal sharing VDD and the power supply signal VDD and the master clock signal MCLK.
  • FIG. 3 illustrates a transmission apparatus for describing in detail a method of transmitting a master clock between systems of the present invention.
  • the inter-system master clock transmission apparatus 200 of the present invention has the same configuration as that of FIG. 2, but includes a second system 230 including a signal adder 235 and a signal separator 215. It further includes a first system 210.
  • a master clock signal MCLK is used by using a power signal sharing transmission line 221 without using a separate master clock signal transmission line 125.
  • the signal adder 235 is provided in the second system 230.
  • the signal adder 235 receives the power signal VDD and the master clock signal MCLK, sums these signals, and adds the synthesized synthesized signal VDD + MCLK. After generation, the signal is transmitted to the signal separator 215 of the first system 210.
  • the signal separator 215 separates the received composite signal VDD + MCLK to generate each of the power separation signal VDD_I and the separated master clock separation signal MCLK_I.
  • the master clock signal MCLK and the power signal VDD must be separated before using the signal separator 215 in the first system 210.
  • the reason for this is as follows. .
  • the first system 210 can not receive it and use it immediately. It can be judged to exist.
  • FIG. 4 is a timing diagram of a power signal and a masker clock when transmitting a master clock between systems according to the present invention.
  • the master clock signal MCLK and the power signal VDD generate a synthesized signal (VDD + MCLK) synthesized with each other through the signal adder 235, and then synthesized again through the signal separator 215. It can be seen that the signal is separated to generate the same power separation signal VDD_I and master clock separation signal MCLK_I as the first power signal VDD and the master clock signal MCLK.

Abstract

According to the present invention, a master clock transmitting apparatus using a shared transmission line transceives, through a transmission line, a master clock signal (MCLK) and a predetermined transmission signal between a first system and a second system adjacent to each other. The master clock transmitting apparatus comprises: a first system (210) for receiving the master clock signal (MCLK) and the transmission signal; a second system (230) for transmitting the master clock signal (MCLK) and the transmission signal; a ground signal transmission line (223) for transceiving a ground signal (VSS) between the first system (210) and the second system (230); and a power signal shared transmission line (221) for transmitting a power signal (VDD) and the master clock signal (MCLK) together. The master clock transmitting apparatus using a shared transmission line according to the present invention is advantageous in that the power signal shared transmission line is arranged between the first system and the second system adjacent to each other so as to transmit the power signal (VDD) and the master clock signal (MCLK) together.

Description

공유된 전송라인을 사용하는 마스터 클럭 전송 장치Master Clock Transmitter Using Shared Transmission Line
본 발명은 마스터 클럭 전송 장치에 관한 것으로, 더욱 상세하게는 서로 이웃한 제1 시스템과 제2 시스템 간에 전원신호(VDD) 및 상기 마스터 클럭신호(MCLK)를 함께 전송하기 위한 전원신호 공유전송라인을 구비하여 별도의 마스터 클럭 전송라인을 필요로 하지 않는 공유된 전송라인을 사용하는 마스터 클럭 전송 장치에 관한 것이다. The present invention relates to a master clock transmission apparatus, and more particularly, to a power signal sharing transmission line for transmitting a power signal VDD and the master clock signal MCLK together between a neighboring first system and a second system. The present invention relates to a master clock transmission apparatus using a shared transmission line that does not require a separate master clock transmission line.
시스템(System)은 일반적으로 시스템의 동작을 위한 마스터 클럭(Master Clock)을 공급받기 위해 시스템 내에 클럭 소스(clock source)를 사용하거나 다른 시스템에서 클럭(clock)을 받게 된다.A system generally uses a clock source in the system to receive a master clock for the operation of the system or receives a clock from another system.
클럭(clock)을 발생시키는 디바이스를 마스터 디바이스(Master Device)라 하며, 클럭(clock)을 수신하는 디바이스를 슬래이브 디바이스(Slave Device)라 하고, 이들은 서로 주종의 관계를 갖는다. A device that generates a clock is called a master device, and a device that receives a clock is called a slave device, and they have a predominant relationship with each other.
한편, 시스템 내부에 클럭 소스(clock source)를 가지고 있는 경우는 상관없지만, 외부에서 클럭(clock)을 받아야만 하는 경우는 클럭(clock) 입력을 위해 전용 라인을 할당해 주어야 한다.On the other hand, it does not matter if you have a clock source inside the system, but if you need to receive a clock from the outside, you need to allocate a dedicated line for clock input.
또한, 보통 시스템의 경우 연결라인을 추가하는데 별다른 문제가 없는 경우는 상관없지만, 2개의 시스템을 최소한의 라인으로 연결 해야만 하는 경우 연결라인의 개수를 줄이는 것은 아주 중요한 문제가 된다.In addition, in the case of a normal system, it is not a problem if there is no problem in adding a connection line, but it is very important to reduce the number of connection lines when two systems must be connected to a minimum line.
도 1은 종래의 시스템 간 마스터 클럭을 전송하는 전송장치를 도시한 것이다. 1 illustrates a transmission apparatus for transmitting a master clock between systems in the related art.
도 1을 참조하면, 종래의 시스템 간 마스터 클럭 전송 장치(100)는 제1 시스템(110), 제2 시스템(130), 전원신호 전송라인(121), 접지신호 전송라인(123) 및 마스터 클럭 전송라인(125)을 포함한다. Referring to FIG. 1, a conventional inter-system master clock transmission apparatus 100 includes a first system 110, a second system 130, a power signal transmission line 121, a ground signal transmission line 123, and a master clock. And a transmission line 125.
제1 시스템(110) 및 제2 시스템(130) 상호 간은 전원신호 전송라인(121)을 통해 전원신호(VDD)를, 접지신호 전송라인(123)을 통해 접지 신호(VDD)를 각각 송 수신 한다.The first system 110 and the second system 130 transmit and receive the power signal VDD through the power signal transmission line 121 and the ground signal VDD through the ground signal transmission line 123, respectively. do.
한편, 제1 시스템(110)은 마스터 클럭 전송라인(125)을 통해 제2 시스템(130)이 전송한 마스터 클럭 신호(MCLK)를 수신한다. Meanwhile, the first system 110 receives the master clock signal MCLK transmitted by the second system 130 through the master clock transmission line 125.
하지만, 종래의 시스템 간 마스터 클럭 전송 장치(100)는 전원신호 전송라인(121), 접지신호 전송라인(123) 외에 별도의 마스터 클럭 전송라인(125)을 사용함으로, 2개의 시스템을 최소 라인으로 연결해야 하는 경우 연결 라인의 개수가 많아짐에 따라 회로가 복잡해지고, 불필요한 전력 손실을 초래하는 문제점이 있었다. However, the conventional inter-system master clock transmission apparatus 100 uses a separate master clock transmission line 125 in addition to the power signal transmission line 121 and the ground signal transmission line 123, thereby making the two systems the minimum line. In the case of connecting, the circuit becomes complicated as the number of connecting lines increases, leading to unnecessary power loss.
본 발명이 해결하고자 하는 기술적 과제는, 서로 이웃한 제1 시스템과 제2 시스템 간에 전원신호(VDD) 및 상기 마스터 클럭신호(MCLK)를 함께 전송하기 위한 전원신호 공유전송라인을 구비하여 별도의 마스터 클럭 전송라인을 필요로 하지 않는 공유된 전송라인을 사용하는 마스터 클럭 전송 장치를 제공하는데 있다. The technical problem to be solved by the present invention is to provide a separate master by having a power signal sharing transmission line for transmitting the power signal (VDD) and the master clock signal (MCLK) together between the neighboring first system and the second system The present invention provides a master clock transmission apparatus using a shared transmission line that does not require a clock transmission line.
상기 기술적 과제를 이루기 위한 본 발명에 따른 공유된 전송라인을 사용하는 마스터 클럭 전송 장치는, 서로 이웃한 제1 시스템과 제2 시스템 간에 마스터 클럭신호(MCLK) 및 소정의 전송신호를 전송라인을 통해 송수신하는 마스터 클럭 전송장치에 있어서, 상기 마스터 클럭신호(MCLK) 및 상기 전송신호를 수신 받는 제1 시스템(210); 상기 마스터 클럭신호(MCLK) 및 상기 전송신호를 송신하는 제2 시스템(230); 상기 제1 시스템(210)과 상기 제2 시스템(230)간에 접지신호(VSS)를 송수신하기 위한 접지신호 전송라인(223); 및 전원신호(VDD) 및 상기 마스터 클럭신호(MCLK)를 함께 전송하기 위한 전원신호 공유전송라인(221)을 제공한다.The master clock transmission apparatus using the shared transmission line according to the present invention for achieving the technical problem, the master clock signal (MCLK) and the predetermined transmission signal between the neighboring first system and the second system through the transmission line A master clock transmission device for transmitting and receiving, comprising: a first system (210) receiving the master clock signal (MCLK) and the transmission signal; A second system 230 for transmitting the master clock signal MCLK and the transmission signal; A ground signal transmission line 223 for transmitting and receiving a ground signal VSS between the first system 210 and the second system 230; And a power signal sharing transmission line 221 for transmitting a power signal VDD and the master clock signal MCLK together.
본 발명은 서로 이웃한 제1 시스템과 제2 시스템 간에 전원신호(VDD) 및 상기 마스터 클럭신호(MCLK)를 함께 전송하기 위한 전원신호 공유전송라인을 구비하여 별도의 마스터 클럭 전송라인을 필요로 하지 않는 장점이 있다. The present invention does not require a separate master clock transmission line by including a power signal sharing transmission line for transmitting the power signal VDD and the master clock signal MCLK together between neighboring first and second systems. There are advantages.
도 1은 종래의 시스템 간 마스터 클럭을 전송하는 전송장치를 도시한 것이다. 1 illustrates a transmission apparatus for transmitting a master clock between systems in the related art.
도 2는 본 발명의 시스템 간 마스터 클럭을 전송하는 개념을 간단히 설명하기 위한 전송장치를 도시한 것이다. FIG. 2 illustrates a transmitter for briefly explaining a concept of transmitting a master clock between systems of the present invention.
도 3은 본 발명의 시스템 간 마스터 클럭을 전송하는 방법을 상세히 설명하기 위한 전송장치를 도시한 것이다. 3 illustrates a transmission apparatus for describing in detail a method of transmitting a master clock between systems of the present invention.
도 4는 본 발명에 의한 시스템 간 마스터 클럭을 전송 시 전원 신호와 마스커 클럭의 타이밍도를 도시한 것이다. 4 is a timing diagram of a power signal and a masker clock when transmitting a master clock between systems according to the present invention.
이하에서는 본 발명의 구체적인 실시 예를 도면을 참조하여 상세히 설명하도록 한다. Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 시스템 간 마스터 클럭을 전송하는 개념을 간단히 설명하기 위한 전송장치를 도시한 것이다. FIG. 2 illustrates a transmitter for briefly explaining a concept of transmitting a master clock between systems of the present invention.
도 2를 참조하면, 본 발명의 시스템 간 마스터 클럭 전송 장치(200)는 제1 시스템(210), 제2 시스템(230), 전원신호 공유전송라인(221) 및 접지신호 전송라인(223)을 포함한다. 2, the inter-system master clock transmission apparatus 200 of the present invention may include a first system 210, a second system 230, a power signal sharing transmission line 221, and a ground signal transmission line 223. Include.
제1 시스템(210)은 DC 전원에 소정의 전송신호 즉 전원신호(VDD), 마스터 클럭 신호(MCLK) 및 접지신호(VSS)를 실어서 제2 시스템(230)에게 전송한다. The first system 210 loads a predetermined transmission signal, that is, a power signal VDD, a master clock signal MCLK, and a ground signal VSS, to the second system 230.
본 발명은 종래와 달리 마스터 클럭 신호(MCLK)가 별도의 마스터 클럭 전송라인(125)을 통해 전송되는 대신 전원신호 공유전송라인(221)을 통해 전원신호(VDD) 및 마스터 클럭 신호(MCLK)를 함께 포함하여 전송됨으로 1개의 전송라인을 줄일 수 있음에 기술적 특징이 있다.Unlike the conventional method, the master clock signal MCLK is transmitted through a separate master clock transmission line 125 and instead of the power signal sharing VDD and the power supply signal VDD and the master clock signal MCLK. There is a technical feature that it is possible to reduce one transmission line by being included together.
도 3은 본 발명의 시스템 간 마스터 클럭을 전송하는 방법을 상세히 설명하기 위한 전송장치를 도시한 것이다. 3 illustrates a transmission apparatus for describing in detail a method of transmitting a master clock between systems of the present invention.
도 3을 참조하면, 본 발명의 시스템 간 마스터 클럭 전송 장치(200)는 도2와 동일한 구성을 갖되, 신호 가산기(235)를 포함하는 제2 시스템(230), 신호 분리기(215)를 포함하는 제1 시스템(210)을 더 구비한다. Referring to FIG. 3, the inter-system master clock transmission apparatus 200 of the present invention has the same configuration as that of FIG. 2, but includes a second system 230 including a signal adder 235 and a signal separator 215. It further includes a first system 210.
이하 본 발명의 신호 가산기(235) 및 신호 분리기(215)를 사용하여 별도의 마스터 클럭신호 전송라인(125)을 사용하지 않고, 전원신호 공유전송라인(221)을 사용하여 마스터 클럭신호(MCLK)를 전송하고, 전송된 신호를 시스템에서 사용하는 원리를 간단히 설명한다.By using the signal adder 235 and the signal separator 215 of the present invention, a master clock signal MCLK is used by using a power signal sharing transmission line 221 without using a separate master clock signal transmission line 125. We will briefly explain the principle of transmitting a signal and using the transmitted signal in a system.
신호 가산기(235)는 제2 시스템(230) 내에 구비되며, 전원신호(VDD) 및 마스터 클럭신호(MCLK)를 수신하여 이들 신호를 서로 가산(sum)하여 합성된 합성신호(VDD+MCLK)를 생성한 후 제1 시스템(210)의 신호 분리기(215)에게 전송한다. The signal adder 235 is provided in the second system 230. The signal adder 235 receives the power signal VDD and the master clock signal MCLK, sums these signals, and adds the synthesized synthesized signal VDD + MCLK. After generation, the signal is transmitted to the signal separator 215 of the first system 210.
신호 분리기(215)는 전송 받은 합성신호(VDD+MCLK)를 분리하여 각각의 전원 분리신호(VDD_I) 및 분리된 마스터 클럭 분리신호(MCLK_I)를 생성한다. The signal separator 215 separates the received composite signal VDD + MCLK to generate each of the power separation signal VDD_I and the separated master clock separation signal MCLK_I.
이와 같이 본 발명의 경우 제1 시스템(210)에 신호 분리기(215)를 더 구비하여 사용하기 전에 반드시 마스터 클럭신호(MCLK) 및 전원신호(VDD)를 분리해 주어야 하는데, 그 이유는 다음과 같다.As described above, in the case of the present invention, the master clock signal MCLK and the power signal VDD must be separated before using the signal separator 215 in the first system 210. The reason for this is as follows. .
즉 전원신호 공유전송라인(221)에 전원신호(VDD) 외에 마스터 클럭신호(MCLK)가 존재할 경우 제1 시스템(210)은 이를 수신하여 곧바로 사용할 수 없는데, 이는 전원 입장에서 보면 노이즈(noise)가 존재하는 것으로 판단할 수 있기 때문이다.That is, when the master clock signal MCLK is present in addition to the power signal VDD in the power signal sharing transmission line 221, the first system 210 can not receive it and use it immediately. It can be judged to exist.
도 4는 본 발명에 의한 시스템 간 마스터 클럭을 전송 시 전원 신호와 마스커 클럭의 타이밍도를 도시한 것이다. 4 is a timing diagram of a power signal and a masker clock when transmitting a master clock between systems according to the present invention.
도 4를 참조하면, 마스터 클럭신호(MCLK)와 전원신호(VDD)가 신호 가산기(235)를 통해 서로 합성된 합성신호(VDD +MCLK)를 생성하고, 신호 분리기(215)를 통해 다시 합성된 신호를 분리하여 처음의 전원신호(VDD) 및 마스터 클럭신호(MCLK)와 동일한 전원 분리신호(VDD_I) 및 마스터 클럭 분리신호(MCLK_I)를 발생함을 확인할 수 있다.Referring to FIG. 4, the master clock signal MCLK and the power signal VDD generate a synthesized signal (VDD + MCLK) synthesized with each other through the signal adder 235, and then synthesized again through the signal separator 215. It can be seen that the signal is separated to generate the same power separation signal VDD_I and master clock separation signal MCLK_I as the first power signal VDD and the master clock signal MCLK.
이상에서는 본 발명에 대한 기술사상을 첨부 도면과 함께 서술하였지만 이는 본 발명의 바람직한 실시 예를 예시적으로 설명한 것이지 본 발명을 한정하는 것은 아니다. 또한 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 이라면 누구나 본 발명의 기술적 사상의 범주를 이탈하지 않는 범위 내에서 다양한 변형 및 모방이 가능함은 명백한 사실이다. In the above description, the technical idea of the present invention has been described with the accompanying drawings, which illustrate exemplary embodiments of the present invention by way of example and do not limit the present invention. In addition, it is apparent that any person having ordinary knowledge in the technical field to which the present invention belongs may make various modifications and imitations without departing from the scope of the technical idea of the present invention.

Claims (4)

  1. 서로 이웃한 제1 시스템과 제2 시스템 간에 마스터 클럭신호(MCLK) 및 소정의 전송신호를 전송라인을 통해 송수신하는 마스터 클럭 전송장치에 있어서,  In the master clock transmission apparatus for transmitting and receiving a master clock signal (MCLK) and a predetermined transmission signal through a transmission line between the neighboring first system and the second system,
    상기 마스터 클럭신호(MCLK) 및 상기 전송신호를 수신 받는 제1 시스템(210);A first system 210 receiving the master clock signal MCLK and the transmission signal;
    상기 마스터 클럭신호(MCLK) 및 상기 전송신호를 송신하는 제2 시스템(230);A second system 230 for transmitting the master clock signal MCLK and the transmission signal;
    상기 제1 시스템(210)과 상기 제2 시스템(230)간에 접지신호(VSS)를 송수신하기 위한 접지신호 전송라인(223); 및 A ground signal transmission line 223 for transmitting and receiving a ground signal VSS between the first system 210 and the second system 230; And
    전원신호(VDD) 및 상기 마스터 클럭신호(MCLK)를 함께 전송하기 위한 전원신호 공유전송라인(221)을 포함하는 것을 특징으로 하는 공유된 전송라인을 사용하는 마스터 클럭 전송 장치.Master signal transmission apparatus using a shared transmission line, characterized in that it comprises a power signal sharing transmission line (221) for transmitting a power signal (VDD) and the master clock signal (MCLK) together.
  2. 제 1항에 있어서, 상기 제2 시스템(230)은, The method of claim 1, wherein the second system 230,
    상기 전원신호(VDD) 및 상기 마스터 클럭신호(MCLK)를 수신하여 서로 가산(sum)하여 합성된 합성신호(VDD+MCLK)를 상기 제1 시스템(210)에게 전송하는 신호 가산기(235)를 더 포함하는 것을 특징으로 하는 공유된 전송라인을 사용하는 마스터 클럭 전송 장치.A signal adder 235 for receiving the power signal VDD and the master clock signal MCLK, adding the sum to each other, and transmitting the synthesized synthesized signal VDD + MCLK to the first system 210 is further included. Master clock transmission apparatus using a shared transmission line comprising a.
  3. 제 2항에 있어서, 상기 제1 시스템(210)은, The method of claim 2, wherein the first system 210,
    상기 전원 신호 공유전송라인(221)을 통해 함께 전송된 상기 합성신호(VDD+MCLK)를 수신하여 상기 전원 신호(VDD) 및 상기 마스터 클럭신호(MCLK) 각각으로 분리하여 전원 분리신호(VDD_I) 및 마스터 클럭 분리신호(MCLK_I)를 각각 생성하는 신호 분리기(215)를 더 포함하는 것을 특징으로 하는 공유된 전송라인을 사용하는 마스터 클럭 전송 장치.Receiving the combined signal (VDD + MCLK) transmitted together through the power signal sharing transmission line 221, and separated into each of the power signal (VDD) and the master clock signal (MCLK) power separation signal (VDD_I) and And a signal separator (215) for generating a master clock separation signal (MCLK_I), respectively.
  4. 제 1항에 있어서, 상기 전송신호는,The method of claim 1, wherein the transmission signal,
    전원 신호(VDD) 및 접지 신호(VSS)를 포함하는 것을 특징으로 하는 공유된 전송라인을 사용하는 마스터 클럭 전송 장치.Master clock transmission apparatus using a shared transmission line, characterized in that it comprises a power signal (VDD) and a ground signal (VSS).
PCT/KR2011/005374 2010-07-21 2011-07-21 Master clock transmitting apparatus using a shared transmission line WO2012011751A2 (en)

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KR1020100070459A KR20120008969A (en) 2010-07-21 2010-07-21 Device for transmitting master clock using shared transmission line

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5452344A (en) * 1992-05-29 1995-09-19 Datran Systems Corporation Communication over power lines
US6657484B1 (en) * 2002-05-30 2003-12-02 Texas Instruments Incorporated System and method for decoupling capacitance for an integrated circuit chip
US20030222695A1 (en) * 2002-05-30 2003-12-04 Texas Instruments Incorporated System and method for distributing a reference clock in an integrated circuit using filtered power supply line

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5452344A (en) * 1992-05-29 1995-09-19 Datran Systems Corporation Communication over power lines
US6657484B1 (en) * 2002-05-30 2003-12-02 Texas Instruments Incorporated System and method for decoupling capacitance for an integrated circuit chip
US20030222695A1 (en) * 2002-05-30 2003-12-04 Texas Instruments Incorporated System and method for distributing a reference clock in an integrated circuit using filtered power supply line

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