WO2012011751A3 - Master clock transmitting apparatus using a shared transmission line - Google Patents
Master clock transmitting apparatus using a shared transmission line Download PDFInfo
- Publication number
- WO2012011751A3 WO2012011751A3 PCT/KR2011/005374 KR2011005374W WO2012011751A3 WO 2012011751 A3 WO2012011751 A3 WO 2012011751A3 KR 2011005374 W KR2011005374 W KR 2011005374W WO 2012011751 A3 WO2012011751 A3 WO 2012011751A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- master clock
- signal
- transmission line
- transmitting apparatus
- shared transmission
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
Abstract
According to the present invention, a master clock transmitting apparatus using a shared transmission line transceives, through a transmission line, a master clock signal (MCLK) and a predetermined transmission signal between a first system and a second system adjacent to each other. The master clock transmitting apparatus comprises: a first system (210) for receiving the master clock signal (MCLK) and the transmission signal; a second system (230) for transmitting the master clock signal (MCLK) and the transmission signal; a ground signal transmission line (223) for transceiving a ground signal (VSS) between the first system (210) and the second system (230); and a power signal shared transmission line (221) for transmitting a power signal (VDD) and the master clock signal (MCLK) together. The master clock transmitting apparatus using a shared transmission line according to the present invention is advantageous in that the power signal shared transmission line is arranged between the first system and the second system adjacent to each other so as to transmit the power signal (VDD) and the master clock signal (MCLK) together.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2010-0068759 | 2010-07-16 | ||
KR1020100070459A KR20120008969A (en) | 2010-07-21 | 2010-07-21 | Device for transmitting master clock using shared transmission line |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2012011751A2 WO2012011751A2 (en) | 2012-01-26 |
WO2012011751A3 true WO2012011751A3 (en) | 2012-05-18 |
Family
ID=45833926
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/KR2011/005374 WO2012011751A2 (en) | 2010-07-21 | 2011-07-21 | Master clock transmitting apparatus using a shared transmission line |
Country Status (2)
Country | Link |
---|---|
KR (1) | KR20120008969A (en) |
WO (1) | WO2012011751A2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5452344A (en) * | 1992-05-29 | 1995-09-19 | Datran Systems Corporation | Communication over power lines |
US6657484B1 (en) * | 2002-05-30 | 2003-12-02 | Texas Instruments Incorporated | System and method for decoupling capacitance for an integrated circuit chip |
US20030222695A1 (en) * | 2002-05-30 | 2003-12-04 | Texas Instruments Incorporated | System and method for distributing a reference clock in an integrated circuit using filtered power supply line |
-
2010
- 2010-07-21 KR KR1020100070459A patent/KR20120008969A/en not_active Application Discontinuation
-
2011
- 2011-07-21 WO PCT/KR2011/005374 patent/WO2012011751A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5452344A (en) * | 1992-05-29 | 1995-09-19 | Datran Systems Corporation | Communication over power lines |
US6657484B1 (en) * | 2002-05-30 | 2003-12-02 | Texas Instruments Incorporated | System and method for decoupling capacitance for an integrated circuit chip |
US20030222695A1 (en) * | 2002-05-30 | 2003-12-04 | Texas Instruments Incorporated | System and method for distributing a reference clock in an integrated circuit using filtered power supply line |
Also Published As
Publication number | Publication date |
---|---|
KR20120008969A (en) | 2012-02-01 |
WO2012011751A2 (en) | 2012-01-26 |
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