WO2012047592A2

WO2012047592A2 - Electronic device including a semiconductor layer and a metal-containing layer, and a process of forming the same

Info

Publication number: WO2012047592A2
Application number: PCT/US2011/053289
Authority: WO
Inventors: Rajesh A. Rao; Leo Mathew
Original assignee: Astrowatt, Inc.
Priority date: 2010-09-27
Filing date: 2011-09-26
Publication date: 2012-04-12
Also published as: TW201314926A; WO2012047592A3

Abstract

An electronic device can include a photovoltaic device. In an embodiment, the photovoltaic device can include homojunction and heterojunction portions that have semiconductor compositions that include silicon. In another embodiment, the photovoltaic device can be a free-standing photovoltaic device that has a curved surface. In a further embodiment, a free-standing photovoltaic device may be flexed, bend, or shaped. Thus, the free-standing photovoltaic device can have a shape that matches more closely a corresponding surface of the electronic device to which the photovoltaic device may be coupled. In an embodiment, a photovoltaic device having a curved surface may be fabricated from a substantially flat substrate, and in another embodiment, a photovoltaic device having a substantially flat surface may be fabricated from a substrate having a non-planar surface.

Description

ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR LAYER AND A METAL- CONTAINING LAYER, AND A PROCESS OF FORMING THE SAME

FIELD OF THE DISCLOSURE

The present invention relates generally to electronic devices including semiconductor layers and metal-containing layers and processes of forming the same.

RELATED ART

Photovoltaic cells can include one or more semiconductor layers and an anode and cathode electrically connected to opposite sides of the cells. Improvements regarding designs and method of forming the cells are desired. BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example and are not limited in the accompanying figures.

FIG. 1 includes an illustration of a cross-sectional view of a portion of a workpiece including a substrate. FIG. 2 includes an illustration of a cross-sectional view of the workpiece of FIG. 1 after a semiconductor layer.

FIG. 3 includes an illustration of a cross-sectional view of the workpiece of FIG. 2 after doping a portion of the semiconductor layer.

FIG. 4 includes an illustration of a cross-sectional view of the workpiece of FIG. 3 after forming a he teroj unction portion of the electronic device in accordance with an embodiment.

FIG. 5 includes an illustration of a cross-sectional view of the workpiece of FIG. 4 after a metal-containing layer.

FIG. 6 includes an illustration of a cross-sectional view of the workpiece of FIG. 5 after creating a weakened region within the workpiece. FIG. 7 includes an illustration of a cross-sectional view of the workpiece of FIG. 6 after separation of a portion of the substrate from a remaining portion of the substrate.

FIG. 8 includes an illustration of a cross-sectional view of the workpiece of FIG. 7 after mounting the portion of the substrate onto a workpiece holder. FIG. 9 includes an illustration of a cross-sectional view of the workpiece of FIG. 6 illustration an orientation of the workpiece during subsequent processing.

FIG. 10 includes an illustration of a cross-sectional view of a substantially completed photovoltaic device in accordance with an embodiment.

FIGs. 11 to 13 include illustrations of portions of electronic devices where photovoltaic devices have been shaped to underlying corresponding surfaces of the electronic device in accordance with embodiments.

Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.

DETAILED DESCRIPTION

The following description in combination with the figures is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings and should not be interpreted as a limitation on the scope or applicability of the teachings. However, other teachings can certainly be utilized in this application.

Before addressing details of embodiments described below, some terms are defined or clarified. The term "free-standing," when referring to an article, such as a photovoltaic device or the like, is intended to mean such an article is capable of maintaining its shape without the assistance of a handling substrate or another object.

The term "metal" and any of its variants are intended to refer to a material that includes an element that is (1) within any of Groups 1 to 12, or (2) within Groups 13 to 15, an element that is along and below a line defined by atomic numbers 13 (Al), 50 (Sn), and 83 (Bi), or any combination thereof. Metal does not include silicon or germanium. Note, however, that a metal silicide is a metallic material. The term "semiconductor composition" is intended to mean that a material, layer, or region includes a particular composition of semiconductor element(s) or compound(s), and excludes dopant(s) within such material, layer, or region. For example, an n-type doped silicon layer may consist of phosphorus and silicon, but the semiconductor composition is solely silicon. Other semiconductor compositions can include silicon germanium, gallium arsenide or the like. Note that a particular crystalline structure, or lack thereof, is not part of the term. Thus, substantially monocrystalline silicon and amorphous silicon have the same semiconductor composition.

The term "substantially transparent" is intended to mean that a layer, an object, or a region can transmit at least 70% of the incident radiation at a particular wavelength or range of wavelengths through such layer, object, or region.

As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having" or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited only to those features but may include other features not expressly listed or inherent to such method, article, or apparatus. Further, unless expressly stated to the contrary, "or" refers to an inclusive-or and not to an exclusive-or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present). Also, the use of "a" or "an" is employed to describe elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. This description should be read to include one or at least one and the singular also includes the plural, or vice versa, unless it is clear that it is meant otherwise. For example, when a single item is described herein, more than one item may be used in place of a single item.

Similarly, where more than one item is described herein, a single item may be substituted for that more than one item.

Group numbers corresponding to columns within the Periodic Table of the elements use the "New Notation" convention as seen in the CRC Handbook of Chemistry and Physics, 81^st Edition (2000-2001). Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. To the extent not described herein, many details regarding specific materials and processing acts are conventional and may be found in textbooks and other sources within the semiconductor and electronic arts.

An electronic device can include a photovoltaic device that includes a heterojunction. In a particular embodiment, the photovoltaic device can include a heterojunction portion having a semiconductor composition that includes a Group 14 element, and a homojunction portion having a semiconductor composition that includes the same or different Group 14 element(s). The homojunction portion can directly contact the heterojunction portion at a heterojunction, and the heterojunction portion has a higher energy bandgap as compared to the homojunction portion. The Group 14 elements include Si, Ge, and C. Such elements, and particularly Si and Ge have electronic properties that are well known and understood. Further, manufacturing may be relatively simpler when semiconductor compositions include Group 14 elements, as compared to ni-V and II-V semiconductor materials. Note that use of materials having semiconductor compositions that include Group 14 element(s) is not required of all embodiments described herein, and therefore, the use of such materials should not be construed as being essential or critical.

In another particular embodiment, the electronic device can include a semiconductor layer, and a metal-containing layer electrically connected to the semiconductor layer. The combination of the semiconductor layer and the metal-containing layer can be curved. Such an electronic device may be flexible and allow the electronic device to be used with a variety of geometric shapes. For example, when the electronic device includes a photovoltaic device, the photovoltaic device may be mounted to a cylinder, and such a cylinder may be partly surrounded by a hemispherical reflector to allow light to be captured at different angles and may allow incident light to be directed at the photovoltaic device at a wider variety of angles. Further, the electronic device may be attached to irregular shapes, rather than being limited to flat surfaces. Still further, the electronic device may be able to withstand more bending and flexing than many conventional photovoltaic cells before the electronic device would become nonfunctional.

In a further particular embodiment, a method of forming the electronic device can include forming a semiconductor layer directly contacting a surface of a substrate, wherein, at the surface, the substrate includes a semiconductor material, and forming a metal-containing layer over the semiconductor layer. The method can further include separating at least a portion of the semiconductor layer and the metal-containing layer from the substrate, wherein substantially none of the substrate is removed with the semiconductor layer and the metal layer. The ability to form the semiconductor layer and not remove a significant portion of the substrate can allow the substrate to be used, in theory, an infinite number of times. Compare such a method to another method in which the semiconductor layer is formed by removing a portion of the substrate. In such other method, a limited number of devices can be formed before the substrate can be no longer used.

Although the description below provides many details, including particular numerical values and configurations, after reading this specification, skilled artisans will appreciate that the embodiments described herein merely illustrate and do not limit the scope of the present invention.

FIG. 1 illustrates a workpiece 100 comprising a substrate 102. The substrate may be a semiconductor substrate comprising a Group 14 element (silicon, germanium, or carbon), any combination of Group 14 elements (silicon germanium, carbon-doped silicon, or the like). In an embodiment, the substrate 102 is substantially monocrystalline, has a semiconductor composition that includes silicon, and can have a thickness of at least approximately 50 microns or at least approximately 200 microns. Although there is no theoretical upper limit on the thickness, the substrate 102 may be no greater than approximately 5 meters or no greater than approximately 0.1 meter. As will be described in an alternative embodiment, ingot processing can be used to form substantially rectangular sheets. In a particular embodiment, the substrate 102 is substantially monocrystalline and may be a semiconductor composition that is solely silicon or silicon germanium. The substrate 102 can have a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³ of an n-type or a p-type dopant. In another embodiment, the substrate 102 can have a dopant concentration of at least approximately lxlO¹⁵ atoms/cm³ of an n-type or a p-type dopant or be undoped.

FIGs. 2 and 3 include illustrations in which a heavily doped region and a substantially lighter doped or undoped region are formed. Referring to FIG. 2, a semiconductor layer 202 is formed over the substrate 102. The semiconductor layer 202 may be doped, undoped, or a combination thereof. The semiconductor layer 202 can have a thickness at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns, and in another embodiment, the semiconductor layer can have a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns. The semiconductor layer 202 may be formed as an epitaxial growth from the substrate. In another embodiment, the semiconductor layer 202 may be deposited as an amorphous or polycrystalline material and annealed to recrystallize the semiconductor layer 202 from the substrate 102.

During an anneal or a subsequent heat cycle, dopant from the substrate 102 can diffuse into the semiconductor layer 202 to form a doped region 302, as illustrated in FIG. 3. In another embodiment, the doped region 302 may be formed by implanting or diffusing a dopant into the substrate 102. The peak dopant concentration of the doped region 302 is at least approximately lxlO¹⁹ atoms/cm³. In another embodiment, the doped region 302 can be formed by epitaxially growing a semiconductor layer from the substrate 102. In a further embodiment, the

semiconductor layer may be doped as grown or may be subsequently doped. Such semiconductor layer will have a peak dopant concentration is at least approximately lxlO¹⁹ atoms/cm³. The doped region 302 may have thickness no greater than approximately 900 nm, no greater than approximately 500 nm, or no greater than 300 nm.

A remaining portion 304 of the semiconductor layer 202 overlies doped portion 302. The remaining portion 304 may be undoped or have a dopant concentration no greater than approximately lxlO¹⁸ atoms/cm³. When doped, the remaining portion and the doped portion 302 have the same conductivity type. In an embodiment, the substrate 102, the doped region 302 and the remaining portion 304 have substantially the same semiconductor composition and are both substantially monocrystalline. In a particular embodiment, the substrate 102, the doped region 302 and the remaining portion 304 include substantially monocrystalline silicon. In another embodiment, another method may be used to form the structure as illustrated in FIG. 3. In alternative embodiment, the semiconductor layer 202 may be formed such that a dopant gas is used during an early portion to form the doped region 302, and subsequently, the dopant gas is turned off or the relative portion of the dopant gas as compared to the

semiconductor gas flow is reduced to form the remaining portion 304. In still another embodiment, a semiconductor layer may be deposited and then subsequently doped after deposition to form the doped region 302. After doping another semiconductor layer can be formed that corresponds to the remaining portion 304.

A heterojunction portion 402 is formed over the semiconductor layer 202, as illustrated in FIG. 4. The heterojunction portion 402 has a higher energy bandgap than the semiconductor layer 202. In an embodiment, the heterojunction portions 402 and the semiconductor layer 202 can have semiconductor compositions that include only one or more Group 14 elements, both of which may include silicon. Monocrystalline Si has an energy bandgap of approximately 1.1 eV, and polycrystalline or amorphous silicon has an energy bandgap in a range of approximately 1.7 eV to approximately 2.1 eV. In a particular embodiment, the semiconductor layer 202 and the heterojunction portion 402 may have semiconductor compositions that include solely silicon. In this particular embodiment, the semiconductor layer 202 can include substantially

monocrystalline silicon, and the heterojunction portion 402 can include polycrystalline or amorphous silicon. Referring to FIG. 4, a semiconductor layer 404 having a higher energy bandgap than the semiconductor layer 202 is formed over the remaining portion of the semiconductor layer 202. A heterojunction is formed at the interface of the remaining portion 304 of the semiconductor layer 202 and the semiconductor layer 404. The semiconductor layer 404 can be deposited as an intrinsic (undoped) amorphous or polycrystalline semiconductor layer. The semiconductor layer 404 may include a single film or a plurality of films having successively different energy bandgaps. The semiconductor layer 404 has a thickness in a range of approximately 2 nm to approximately 10 nm.

A doped region 406 is formed from a portion of the semiconductor layer 404 or deposited as a separate doped semiconductor layer. The doped region 406 has a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³. In a particular embodiment, the doped region 406 comprises heavily doped p-type silicon. The doped region 406 is deposited a thickness in a range of approximately 3 nm to approximately 30 nm. In one embodiment, the semiconductor layer 404 is not implemented in the heterojunction portion 402, and the doped region 406 is formed directly over the remaining portion 304 of the semiconductor layer 202.

In an alternative embodiment, a semiconductor layer may have a thickness of the combination of the semiconductor layer 404 and the doped region 406, both as previously described. In an embodiment, the thickness is in a range of approximately 6 nm to approximately 30 nm. A portion of the semiconductor layer can be doped to form a doped region 406 and a remaining portion that corresponds to the semiconductor layer 404, as previously described.

If needed or desired the topology of the remaining portion 304 of the semiconductor layer 202 may be modified to aid in reflection or in junction formation. The varying topology can be formed by a process including anodization, lithographic or litholess patterning, imprinting, another suitable technique or any combination thereof. Wet etching may be performed using a basic solution (KOH, NaOH, N(CH₃)₄OH, or the like), a colloidal metal-aided etching solution, another suitable wet etchant, or the like. Alternatively, dry etching may be performed, such as reactive ion etching, sputter etching, laser texturing, or any combination thereof. In a further alternative embodiment, a mechanical removal technique may be used. Such topology modification can substantially improve the reflection and current collection capabilities of the electronic device, such as a solar cell.

A metal-containing layer 502 is formed over the doped region 406, as illustrated in FIG. 5. The metal-containing layer 502 can include an adhesion film, a barrier film, a seed film, another suitable film, or any combination thereof. The adhesion film can include a refractory metal (titanium, tantalum, tungsten, or the like), and the barrier film can include a metal nitride (TiN, TaN, WN of the like) or a metal semiconductor nitride (TaSiN, WSiN, or the like). The seed film can include a transition metal or transition metal alloy, and in a particular embodiment, the seed film can include titanium, nickel, palladium, tungsten, copper, silver, or gold. In other embodiments, other materials may be used within the adhesion film, barrier film, seed film, or any combination thereof. The metal-containing film can be formed by physical vapor deposition (PVD, such as evaporation or sputtering), chemical vapor deposition (CVD), atomic layer deposition (ALD), electrochemistry, another suitable method, or any combination thereof. In another embodiment, the metal-containing film may be bonded to the doped region 406 by forming a metal film over the workpiece and reacting the metal-containing film to form a metal silicide from exposed portions of the doped region 404. Unreacted portions of the metal- containing film, if any, may be removed. In an embodiment, the metal-containing film can have a thickness of at least approximately 1 nm or at least approximately 10 nm, and in another embodiment, the metal-containing film 502 may have a thickness no greater than approximately 10 microns or no greater than approximately 0.1 microns. A conductive film is plated (electroplating, electroless plating, or any combination thereof) over the heterojunction portion 402. The conductive film can have a relatively higher conductance as compared to the other metal-containing film in the metal-containing layer 502. In a particular embodiment, the conductive film is at least approximately 11 times, approximately 50 times, or approximately 500 times thicker than the other metal-containing film. The conductive film may include any of the metals or metal alloys previously described with respect to the other metal-containing film. In a particular embodiment, the conductive film comprises tin, nickel, chromium, copper, silver, gold, or a combination thereof. Similar to the other metal-containing film, the conductive film can include a single film or a plurality of films. In a particular embodiment, the conductive film can consist essentially of gold or nickel, and in another embodiment, the conductive film can be mostly copper with a relatively thin indium-tin alloy to help improve soldering during a subsequent bonding operation. Other combinations of materials can be used such that the composition of the conductive film is tailored to a particular application. In an embodiment, the conductive film, and accordingly, the metal-containing layer 502, can have a thickness of at least approximately 1 micron or at least approximately 30 microns, and in another embodiment, the substantially thicker metal-containing film, and accordingly, the metal-containing layer 502 can have a thickness no greater than approximately 2 mm or no greater than approximately 100 mm.

In one embodiment, the conductive film can create stresses within the workpiece 100 at a location 602, as illustrated in FIG. 6. As will be described later, these stresses can help separate a portion of the workpiece, in the form of a semiconductor layer, from the substrate 102. In a particular embodiment, the stresses are created within the substrate by an annealing process involving a change in temperature of the workpiece 100. The annealing process can be controlled based on the uniformity and defect levels desired in the workpiece 100. The annealing temperature may be determined at least in part on the composition of the substrate 102 and layers of the workpiece 100. In an embodiment, the anneal is performed at a temperatures of at least approximately 25 °C or at least approximately 100 °C, and in another embodiment, the anneal is performed at a temperature no greater than approximately 700 °C or no greater than

approximately 500 °C. In an embodiment, the anneal is performed for a time of at least approximately 1 second or at least approximately 1 hour, and in another embodiment, the anneal is performed for a time no greater than approximately 20 hours or no greater than approximately 6 hours.

In another embodiment, the conductive film can be formed such that a separation- enhancing species is incorporated within the conductive film when it is formed. The separation- enhancing species can help separate a portion of the semiconductor layer 202 or the substratel02 from a remaining portion of the substrate 102. In a particular embodiment, the separation- enhancing species is hydrogen. Hydrogen may be incorporated within the conductive film from the plating bath, such as an acidic solution.

FIG. 6 illustrates the workpiece after the stresses are created in the workpiece and the separation-enhancing species is diffused, transported, or otherwise moved from the metal- containing layer 502 into the heterojunction portion 402, semiconductor layer 202, and potentially, into the substrate 102 of the workpiece. The movement of the separation-enhancing species can aid in separating a combination of the metal-containing layer 502, heterojunction portion 402, and the semiconductor layer 202 from the substrate 102. In one embodiment, the movement of the separation-enhancing species can be accomplished by the annealing process used to create the stresses in the substrate as described previously.

The temperature and time of the anneal can depend on the particular application for the semiconductor device being formed. The thickness of the semiconductor layers of the electronic device being formed may be based at least on part on the composition of homojunction portion 404, the semiconductor layer, 202, and the substrate 102 and the particular electronic application, such as a photovoltaic cell or the like. As the desired thickness increases, the anneal temperature, the anneal time, or a combination of the anneal temperature and time may increase, and conversely, as the thickness decreases, the anneal temperature, the anneal time, or a combination of the anneal temperature and time may decrease. Note that even though the metal-containing layer 502 may include a barrier film, such barrier film helps to reduce the likelihood that a metallic material from the conductive film from entering the substrate 102. However, the separation-enhancing species may diffuse or otherwise migrate through the barrier film. Thus, a barrier film is effectively a barrier to the metallic material within the conductive film and not a barrier to the separation-enhancing species.

In another embodiment, the plating may be performed using a plating bath maintained at a temperature higher than room temperature (for example, approximately 20 °C), for example in a range of approximately 40 °C to approximately 95°C. After plating the conductive film, the workpiece 100 can be cooled to a temperature closer to room temperature. In any of the previously described embodiments during or following plating the conductive film, the conductive film is exposed to a temperature change that can include cooling, heating, or a combination of heating followed by cooling.

As illustrated in FIG. 6, such a temperature change can create a weakened region at the location 602 within the workpiece due to a combination of the stresses within the substrate and movement of the separation-enhancing species. In an embodiment, the location 602 can be at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns from the surface of the metal-containing layer 502 closest to the substrate 102, and in another embodiment, the location 602 may be no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns from the surface of the metal-containing layer 502. The location 602 may correspond to a location where the doped region 302 directly contacts the substrate 102, or the location 602 may correspond to a location where the remaining portion 304 directly contacts the doped region 302. In still other embodiments, the location 602 may be completely within the doped region 302 or within the substrate 102 at a location close to the doped region 302.

Accordingly, such a temperature change can help to separate the combination of the metal-containing layer 502, the he teroj unction portion 402 and a homojunction portion from the substrate 102, as illustrated in FIG. 7. The homojunction portion can include the semiconductor layer 202. In another embodiment, the homojunction portion may include a portion of the substrate 102, and in another embodiment may include the remaining portion 304 of the semiconductor layer 202 but not the doped region 302. If the doped region 302 is not removed with the metal-containing layer 502, a newly formed surface of the remaining portion 403 may be doped to allow an ohmic contact to be formed to a subsequently-formed electrode. The location 602 in FIG. 6 represents a weak point from which separation may occur, and a combination of the heterojunction portion 402 and the homojunction portion can have a thickness at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns, and in another embodiment, the combination can have a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns. The separation may occur during the cooling, heating, or a combination of heating followed by cooling or thereafter. In an embodiment, the separation may occur by spalling without using a mechanical operation. In another embodiment, a mechanical operation may be used to help with the separation. In a particular embodiment, the separation may occur by cleaving or fracturing the workpiece at or near the location 402. A wedge, wire, or saw may be used to aid in the mechanical separation. In another embodiment, a metallic paste can be mechanically applied over the workpiece, and a stiffened or handling substrate can be attached to the metallic paste and used to aid the separation operation. In a particular embodiment, the separation can be analogous to an exfoliation operation. The separated portion of the device may remain attached to the handling substrate or may be removed. Because the metal-containing layer provides sufficient mechanical support, the partially formed device may be free standing. As illustrated in FIG. 7, a combination 702 of the homojunction and heterojunction portions remains bonded to the portion of the workpiece that includes the metal-containing layer 502. The combination 702 and the metal-containing layer 502 are thick enough to be handled mechanically for further processing. In the embodiment illustrated, the workpiece has a concave surface and a convex surface opposite the concave surface. The metal-containing layer 502 is disposed at the concave surface, and the combination 702 is disposed at the convex surface.

The curvature may be characterized by a vertical displacement per unit of lateral dimension associated with the curve. As illustrated in FIG. 7, dimension 722 corresponds to the vertical displacement, and dimension 724 corresponds to the lateral dimension. In an embodiment, a ratio of the lateral dimension to the vertical displacement is at least approximately 1: 1, at least approximately 2: 1, or at least approximately 4: 1, and in another embodiment, the ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1. In another embodiment, the ratio may be higher or lower than the values described without departing from the concepts as described herein.

The combination 702 and the metal-containing layer 502 can be mounted to a workpiece holder 802 for subsequent processing, as illustrated in FIG. 8. The workpiece holder 802 may help to keep the combination 702 and the metal-containing layer 502 relatively flat during subsequent processing. The workpiece holder 802 may have a coating including a fluoropolymer, a silicon nitride, a silicon carbide, anodized aluminum or the like. In one embodiment, workpiece holder 802 may include a magnet, such an electromagnet. The metal-containing layer 502 may be attracted to the magnet. In another embodiment, an adhesive compound, double-sided adhesive tape, or the like may be used to adhere the metal-containing layer 502 to the workpiece holder 802. In a further embodiment, a mechanical clamp, such as clips, an annular ring, or the like, may be used to secure the combination 702 and the metal-containing layer 502 to the workpiece holder 602.

FIG. 9 includes an illustration of the workpiece in accordance with an embodiment after the separation has occurred. In this embodiment, the workpiece includes the homojunction portion 902, which includes the doped region 302 and the remaining portion 304; the heterojunction portion 402, which includes the semiconductor layer 404 and the doped region

406; and the metal-containing layer 502. The substrate 102 is not illustrated in FIG. 9 and may be reused to form another electronic device. In FIG. 9, a homojunction portion 902 includes substantially the same semiconductor composition and crystal structure. The dopants in the doped region 302 and the remaining portion 304 may be the same or different and still form the homojunction portion 902. Because the doped region 302 has a higher dopant concentration than the remaining portion 304, the homojunction portion 902 has a high-low configuration.

An electrode 1002 can be formed over the doped region 302, as illustrated in FIG. 10. The electrode 1002 can include a principal conductor 1006, and if needed or desired, a conductive layer 1004. The conductive layer 1004 may be disposed along the light-receiving side of the electronic device and can be substantially transparent to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm. The conductive layer 1004 can include indium- tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof. The thickness of the conductive layer 1004 may be selected to ensure a substantial amount of light can be transmitted through the conductive layer 1004. The principal conductor 1006 can include a metal-containing material, such as aluminum, copper, nickel, gold, silver, another suitable metal or metal alloy, or any combination thereof. Unlike the electrode 1004, the principal conductor can be substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm and does not need to be substantially transparent to such radiation. Thus, the principal conductor 1006 may be substantially thicker than the electrode 1002. The thickness of the principal conductor 1006 may be at least approximately 100 nm. The principal conductor 1006 can be a patterned layer that defines openings through which radiation may pass to the underlying semiconductor layers. The principal conductor 1006 can have a pattern in the form of strips, a grid, serpentine lines, or another suitable pattern. At this point in the process, a substantially-completed photovoltaic device is formed. The electrode 1002 can be electrically connected to an anode terminal, and the metal- containing layer 502 can be electrically connected to a cathode terminal. When the electronic device is exposed to sunlight, the electronic device can generate electricity.

The photovoltaic cell may be implemented into an electronic device, such as a photovoltaic apparatus. The photovoltaic device can be a free-standing photovoltaic device and does not need to be attached at substantially all times to a relative stiff substrate. Further, the free-standing photovoltaic device may be flexed, bent, shaped, or any combination thereof, as needed or desired, while still remaining operational. The ability to flex, bend, or shape the freestanding photovoltaic device allows it to be used significantly different surface topologies of the electronic device. In an embodiment, the free-standing photovoltaic device can be shaped to match more closely the corresponding surface of the electronic device. The corresponding surface of the electronic device can be non-planar, such as curved, irregular, have an abrupt surface feature, such as a corner, a ridge, or the like. The abrupt surface feature may not be represented as a continuous mathematical function. The ability to shape the electronic device greatly improves the ability to implement the electronic device in apparatuses having a wide variety of different surface shapes.

The photovoltaic device can be coupled to a corresponding surface of the electronic device. In an embodiment, the photovoltaic device can be removably coupled to the

corresponding surface of the electronic device. For example, the photovoltaic device may be fastened or otherwise secured into place. The electronic device may later be disassembled to allow the photovoltaic device to be removed. In another embodiment, the photovoltaic device can be permanently coupled to the corresponding surface of the electronic device. A metal-containing epoxy or other conductive bonding agent may be used to permanently attach the photovoltaic device to the electronic device. In an embodiment, the coupling can include direct contact between the photovoltaic device and the corresponding surface of the electronic device. In another embodiment, as illustrated in FIG. 11, a layer 1104 may be disposed between the photovoltaic device 1104 and the corresponding surface of the electronic device 1102. In an embodiment, the layer 1104 includes an adhesive material, and in another embodiment, the layer 1104 includes an interposer having z- axis conductors. In another embodiment, a different type of layer may be used.

In FIG. 11, an electronic device 1100 can include a portion 1102 that has a curved surface that is to receive a photovoltaic device 1106. Such a curved surface may be part of a cylinder. The photovoltaic device 1106 in accordance with any of the previously described embodiments can be coupled to the corresponding curved surface of the electronic device. A layer 1104 may be disposed between the portion 1102 and the photovoltaic device 1106. If needed or desired, one or more additional photovoltaic devices may also be attached to the portion 1102 of the electronic device. In this embodiment, the electronic device 1100 can include one or more cylinders that are partly surrounded by hemispherical reflectors. In other embodiments, the electronic device may have more challenging surface topologies. In FIG. 12, an electronic device 1200 can include a portion 1202 that has an irregular surface. As illustrated, the corresponding surface of the portion 1202 is an undulating surface. A photovoltaic device 1206 in accordance with any of the previously described embodiments can be shaped to match more closely the corresponding surface of the portion 1202. The photovoltaic device 1206 can be coupled to the corresponding surface of the electronic device. A layer 1204 may be disposed between the portion 1202 and the photovoltaic device 1202. In FIG. 13, an electronic device 1300 can include a portion 1302 that has a corresponding surface with an abrupt feature 1322. A photovoltaic device 1206 in accordance with any of the previously described embodiments can be shaped to match more closely the corresponding surface of the portion 1302 and cover the abrupt feature 1322, such as a corner or a ridge. The photovoltaic device 1306 can be coupled to the corresponding surface of the electronic device. A layer 1304 may be disposed between the portion 1202 and the photovoltaic device 1306. Thus, a photovoltaic device in accordance with the embodiments described herein may be flexed, bent, or shaped to conform to a variety of different surface topologies. The process are previously described may be performed using a substrate a wafer form and produce substantially circular disk-shaped devices. In another embodiment, the substrate may be in an ingot form. In a particular embodiment the ingot can be substantially cylindrical and have a diameter of approximately 50 mm to approximately 300 mm or even larger. The length of the ingot can be greater than the diameter and can range from approximately 150 mm to approximately 5 meters. The process as described with respect to the FIGs. 1 to 7 is performed. Before plating the conductive film of the metal-containing layer 502, a portion of the metal- containing film of the metal-containing layer 302 may be removed or covered with a relatively narrow strip (that is, the width of the strip is substantially less than the circumference of the ingot) of an insulator to substantially prevent the conductive film from plating completely around the ingot. The lack of plating around a complete circumference of the ingot may create a relative weak spot from which the semiconductor layer 202 may be removed from a remainder of the ingot. In another embodiment, the metal-containing layer 502 may be scored or cut along part of all of a length of the ingot to aid in the separation. The ingot may be beneficial to produce a photovoltaic device that is substantially rectangular in shape. Embodiments in accordance with the concepts as described herein can be particularly beneficial. Electronic devices can be formed where the substrate is not significantly consumed when forming at least approximately 110 electronic devices from a single substrate. The separation operation may be targeted, an average, to correspond to a location where the doped region 302 of the semiconductor layer 202 contacts the substrate 102. For particular electronic devices, some of the doped regions 302 may remain with the substrate, and with others, some of the substrate 102 may be removed. Overall, the thickness of the substrate may vary by no greater than approximately 9% from of originally thickness of the substrate before forming any of the electronic devices. The thickness of the substrate may vary by no greater than approximately 9% from of originally thickness after forming at least approximately 300 electronic devices, at least 500 electronic devices, at least 1100 electronic device, or even more electronic devices.

The electronic device may have all semiconductor layers having semiconductor compositions that include silicon. Silicon sources are readily available as a starting material and for depositing a semiconductor layer. Further, silicon as a semiconductor material is well characterized for its properties, include electronic, chemical and mechanical properties, properties. Thus, the electronic devices can be fabricated using existing materials and processes.

The electronic devices fabricated as stand-alone photovoltaic devices that can be incorporated into electronic devices that have non-planar surfaces. The ability to use the photovoltaic devices has been previously addressed. Because photovoltaic devices, as described herein, may be bent or flexed, such devices may be used where other photovoltaic devices may not. For example, the ability to shape a photovoltaic device may allow a photovoltaic device to span across a ridge or rake of a roof and remain operational.

Further, most fabrication equipment is designed for flat and not curved surfaces. Even through the photovoltaic device may be relatively flat when being formed, such a photovoltaic device formed in accordance with embodiments as described herein can be flexed and bent into a variety of positions. Thus, a surface of the photovoltaic device can be curved when due to the stress at the interface between the heterojunction portion 402 and the semiconductor layer 502. In another embodiment, a photovoltaic device can be fabricated from a curved surface and be mounted in a photovoltaic apparatus along a flat surface. For example, a photovoltaic device may be fabricated from a cylindrical ingot. When the photovoltaic device separates from the cylindrical ingot, the photovoltaic device may be flattened and result in a rectangular shaped photovoltaic device. The rectangular shape may be useful when the photovoltaic device is implemented in a photovoltaic apparatus having a rectangular shaped light-receiving surface. While benefits have been described with respect to particular embodiments, such benefits are not required of all embodiments. For example, the photovoltaic devices do not require a heterojunctions. For example, the curved surface after separation and the ability to bend, flex, and shape a free-standing photovoltaic device may be used with a homojunction device. Further, a photovoltaic device that includes a homojunction and heterojunction portions having semiconductor compositions that include silicon does not need to be curved or be flexible, bendable, readily shaped, or the like.

Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. After reading this specification, skilled artisans will appreciate that those aspects and embodiments are only illustrative and do not limit the scope of the present invention.

In a first aspect, an electronic device can include a photovoltaic device. The photovoltaic device can include a heterojunction portion having a semiconductor composition that includes silicon and a homojunction portion having a semiconductor composition that includes silicon. The homojunction portion can directly contact the heterojunction portion at a heterojunction; and the heterojunction portion can have a higher energy bandgap as compared to the homojunction portion.

In an embodiment of the first aspect, the homojunction portion includes a layer having a substantially monocrystalline structure. In a particular embodiment, the heterojunction portion is amorphous, polycrystalline, or a combination of thereof. In another particular embodiment, the homojunction portion and the heterojunction portion have substantially a same semiconductor composition. In still another particular embodiment, the semiconductor composition of the heterojunction portion and the semiconductor composition of the homojunction portion include only one or more Group 14 elements. In another embodiment, the semiconductor composition of the heterojunction portion and the semiconductor composition of the homojunction portion include solely silicon. In still another embodiment, the heterojunction portion has a thickness of at least approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm. In yet another embodiment, the heterojunction portion has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm. In a further embodiment of the first aspect, the heterojunction portion includes a plurality of layers. In a particular embodiment, the heterojunction portion includes an undoped semiconductor layer. In a more particular embodiment, the heterojunction portion further includes a doped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of the homojunction portion. In an even more particular embodiment, the homojunction portion includes a first doped region having a doping concentration no greater than approximately lxlO¹⁸ atoms/cm³, wherein the heterojunction is at the junction of the undoped semiconductor layer and the first doped region; and a second doped region spaced apart from the heterojunction portion and having a doping concentration of at least approximately lxlO¹⁹ atoms/cm³. In another even more particular embodiment, the homojunction portion includes an n- type substantially monocrystalline semiconductor layer, the doped semiconductor layer includes a p-type semiconductor layer, the heterojunction is at a junction of the n-type substantially monocrystalline semiconductor layer and the undoped semiconductor layer, and the undoped semiconductor layer is an only layer disposed between the n-type substantially monocrystalline semiconductor layer and the p-type semiconductor layer.

In yet a further embodiment of the first aspect, the homojunction portion has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns. In another embodiment, the homojunction portion has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

In still another embodiment of the first aspect, the photovoltaic device further includes an electrode electrically connected to the homojunction portion. In a particular embodiment, the electrode includes a principal conductor that is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm. In a more particular embodiment, the principal conductor is in a form of a grid. In another more particular embodiment, the electrode further includes a conductive layer that is substantially transparent to the radiation. In an even more particular embodiment, the conductive layer includes indium-tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof. In another even more particular embodiment, the conductive layer is disposed between the principal conductor and the homojunction portion.

In another embodiment of the first aspect, the electronic device further includes a metal- containing layer electrically connected to the heterojunction region, wherein the metal-containing layer contacts substantially all of a surface of the heterojunction region. In a particular embodiment, the metal-containing layer has a thickness of at least approximately 11 microns, at least approximately 30 microns, or at least approximately 50 microns. In another particular embodiment, the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than approximately 200 microns. In still another particular embodiment, the metal containing layer includes a conductive film including 100 %, at least 99%, at least 95%, or at least 90% of a total thickness of the metal-containing layer. In a more particular embodiment, the metal-containing layer further includes an adhesion film, a barrier film, a seed film, or any combination thereof. In yet another particular embodiment, the heterojunction portion has a surface with a varying topology. In a more particular embodiment, the metal-containing layer is disposed along the surface with the varying topology.

In still another embodiment of the first aspect, the photovoltaic device is a free-standing photovoltaic device that is curved. In a particular embodiment, the photovoltaic device has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is at least approximately 1 : 1, at least approximately 2: 1, or at least approximately 4: 1. In another particular embodiment, the photovoltaic device has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1. In a more particular embodiment, the photovoltaic device has concave surface and a convex surface opposite the concave surface. In an even more particular embodiment, as compared to the heterojunction portion, the homojunction portion is disposed closer to the concave surface; and as compared to the homojunction portion, the heterojunction portion is disposed closer to the convex surface.

In a second aspect, an electronic device can include a photovoltaic device. The photovoltaic device can include a semiconductor layer and a metal-containing layer electrically connected to the semiconductor layer, wherein a combination of the semiconductor layer and the metal-containing layer is part of a free-standing photovoltaic device that is curved. In an embodiment of the second aspect, the photovoltaic device has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is at least approximately 1: 1, at least approximately 2: 1, or at least approximately 4: 1. In another embodiment, the photovoltaic device has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1. In still another embodiment, the photovoltaic device has concave surface and a convex surface opposite the concave surface. In a particular embodiment, as compared to the semiconductor layer, the metal-containing layer is disposed closer to the concave surface; and as compared to the metal-containing layer, the semiconductor layer is disposed closer to the convex surface.

In a further embodiment of the second aspect, the free-standing photovoltaic cell is capable of being flexed, bent, shaped, or any combination thereof. In still a further embodiment, the metal-containing layer has a thickness of at least approximately 11 microns, at least approximately 30 microns, or at least approximately 50 microns. In yet a further embodiment, the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than approximately 200 microns. In another embodiment, the metal containing layer includes a conductive film including 100 %, at least 99%, at least 95%, or at least 90% of a total thickness of the metal-containing layer. In a particular embodiment, the metal-containing layer further includes an adhesion film, a barrier film, a seed film, or any combination thereof.

In still another embodiment of the second aspect, the photovoltaic device further includes an electrode, wherein, as compared to the metal-containing layer, the electrode is closer to a light- receiving surface of the photovoltaic device. In a particular embodiment, the electrode includes a principal conductor that is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm. In a more particular embodiment, the principal conductor is in a form of a grid. In another more particular embodiment, the electrode further includes a conductive layer that is substantially transparent to the radiation. In an even more particular embodiment, the conductive layer is disposed between the principal conductor and the semiconductor layer. In yet an even more particular embodiment, the conductive layer includes indium-tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof.

In yet another embodiment of the second aspect, the electronic device further includes a homojunction portion and a heterojunction portion, wherein a heterojunction is formed at an interface between the homojunction and heterojunction portions, and the homojunction portion includes the semiconductor layer. In a particular embodiment, the semiconductor layer has a substantially monocrystalline structure and a semiconductor composition that includes silicon. In a more particular embodiment, the heterojunction portion is amorphous, polycrystalline, or a combination of thereof. In another more particular embodiment, the heterojunction portion includes a layer having a semiconductor composition that includes silicon. In still another more particular embodiment, the homojunction portion and the heterojunction portion have substantially a same semiconductor composition. In a further more particular embodiment, the semiconductor composition of the heterojunction portion and the semiconductor composition of the homojunction portion include only one or more Group 14 elements. In still a further more particular embodiment, the semiconductor composition of the heterojunction portion and the semiconductor composition of the homojunction portion include solely silicon.

In another particular embodiment of the second aspect, the heterojunction portion has a higher energy bandgap as compared to the semiconductor material of the homojunction portion. In still another particular embodiment, the heterojunction portion has a thickness of at least approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm. In yet another particular embodiment, the heterojunction portion has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm. In a further particular embodiment, the heterojunction portion includes a plurality of layers. In a more particular embodiment, the heterojunction portion includes an undoped semiconductor layer. In an even more particular embodiment, the heterojunction portion further includes a doped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of the homojunction portion. In still an even more particular embodiment, the homojunction portion includes a first doped region having a doping concentration no greater than approximately lxlO¹⁸ atoms/cm³, wherein the heterojunction is at the junction of the undoped semiconductor layer and the first doped region; and a second doped region spaced apart from the heterojunction portion and having a doping concentration of at least approximately lxlO¹⁹ atoms/cm³. In yet an even more particular embodiment, the homojunction portion includes an n-type substantially monocrystalline semiconductor layer, the doped semiconductor layer includes a p-type semiconductor layer, the heterojunction is at a junction of the n-type substantially monocrystalline semiconductor layer and the undoped semiconductor layer, and the undoped semiconductor layer is an only layer disposed between the n-type substantially monocrystalline semiconductor layer and the p-type semiconductor layer.

In a further particular embodiment of the second aspect, the homojunction portion includes a doped region having a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³. In still a further particular embodiment, the homojunction portion has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns. In yet a further particular embodiment, the homojunction portion has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

In a third aspect, a method of forming an electronic device including a photovoltaic device can include forming a semiconductor layer directly contacting a surface of a substrate, wherein, at the surface, the substrate includes a semiconductor material. The method can further include forming a metal-containing layer over the semiconductor layer and separating at least a portion of the semiconductor layer and the metal-containing layer from the substrate, wherein substantially none of the substrate is removed with the semiconductor layer and the metal layer.

In an embodiment of the third aspect, the semiconductor layer and the semiconductor material have substantially a same semiconductor composition. In a particular embodiment, the semiconductor compositions of the semiconductor layer and the semiconductor material include only one or more Group 14 elements. In a more particular embodiment, the semiconductor compositions of the semiconductor layer and the semiconductor material include solely silicon. In still another embodiment, each of the semiconductor layer and the semiconductor material has a substantially monocrystalline structure and a semiconductor composition that includes silicon.

In yet another embodiment of the third aspect, the at least a portion of the semiconductor layer has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns. In a further embodiment, the at least a portion of semiconductor layer has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns. In still a further embodiment, the metal-containing layer has a thickness of at least approximately 11 microns, at least approximately 30 microns, or at least approximately 50 microns. In yet a further embodiment, the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than approximately 200 microns.

In another embodiment of the third aspect, forming the metal containing layer includes plating a conductive film including 100 %, or at least 99%, or at least 95%, or at least 90% of a total thickness of the metal-containing layer. In a particular embodiment, forming the metal- containing layer further includes forming an adhesion film, a barrier film, a seed film, or any combination thereof, before plating the conductive film.

In still another embodiment of the third aspect, the method further includes forming a heterojunction portion before forming the metal-containing layer, wherein a homojunction portion includes the semiconductor layer, and a heterojunction lies at an interface between the homojunction portion and the heterojunction portion. In a particular embodiment, the homojunction portion includes the semiconductor layer having a substantially monocrystalline structure and a semiconductor composition that includes silicon. In a more particular embodiment, the heterojunction portion is deposited as an amorphous layer or a polycrystalline layer. In another more particular embodiment, the homojunction portion and the heterojunction portion have substantially a same semiconductor composition. In still another more particular embodiment, the semiconductor composition of the heterojunction portion and the semiconductor composition of the homojunction portion include only one or more Group 14 elements. In yet another more particular embodiment, the semiconductor composition of the heterojunction portion and the semiconductor composition of the homojunction portion include solely silicon.

In a further particular embodiment of the third aspect, the heterojunction portion has a higher energy bandgap as compared to the homojunction portion. In still a further particular embodiment, the heterojunction portion includes forming a plurality of layers. In a more particular embodiment, forming the heterojunction portion includes forming an undoped semiconductor layer. In an even more particular embodiment, forming the heterojunction portion further includes forming a doped semiconductor layer over the undoped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of the first semiconductor layer. In another more particular embodiment, the heterojunction portion has a thickness of at least approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm. In still another more particular embodiment, the heterojunction portion has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm. In yet another more particular embodiment, forming the heterojunction portion is performed using a chemical vapor deposition technique or a physical vapor deposition technique. In an even more particular embodiment, chemical vapor depositing includes plasma- enhanced chemical vapor deposition, remote plasma chemical vapor deposition, hot wire chemical vapor deposition, low pressure chemical vapor deposition, atmospheric chemical vapor deposition, or any combination thereof. In another particular embodiment of the third aspect, the method further includes forming an electrode adjacent to the at least a portion of the semiconductor layer. In a more particular embodiment, forming the electrode includes forming a principal conductor over the at least a portion of the semiconductor layer, wherein the principal conductor is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm. In an even more particular embodiment, the principal conductor is in the form of a grid. In another even more particular embodiment, forming electrode further includes forming a conductive layer that is substantially transparent to the radiation, wherein forming the conductive layer is performed before forming the principal conductor. In a still further even more particular embodiment, the conductive layer includes indium-tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof along a surface of the homojunction portion.

In a further particular embodiment of the third aspect, the method further includes modifying a topology of an exposed surface at or adjacent to the heterojunction portion before plating the metal-containing layer. In a more particular embodiment, modifying the topology includes wet etching the exposed surface. In an even more particular embodiment, wet etching is performed using a basic solution, a colloidal metal solution, or any combination thereof. In another more particular embodiment, modifying the topology includes dry etching the exposed surface. In an even more particular embodiment, dry etching is performed using a reactive ion etch, a sputter etch, or any combination thereof. In still another more particular embodiment, modifying the topology includes mechanically removing a portion of the substrate at the exposed surface. In an even more particular embodiment, mechanical removing includes cutting groove or a pattern into a material at the exposed surface, abrading the exposes surface, or any combination thereof.

In another embodiment of the third aspect, the method further includes forming a doped region within the semiconductor layer, wherein the doped region has a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³. In a particular embodiment, forming the doped region includes diffusing dopant from the substrate. In another particular embodiment, forming the doped region includes epitaxially growing a first portion of the semiconductor layer from the substrate. In an even more particular embodiment, forming the semiconductor layer further includes epitaxially growing a second portion of the semiconductor layer, wherein the second portion is undoped or has a lower dopant concentration than the first portion of semiconductor layer or is substantially undoped.

In still another embodiment of the third aspect, the method further includes cooling the metal-containing layer, the semiconductor layer, and the substrate after forming the metal- containing layer and before separating the at least a portion of the semiconductor layer. In a particular embodiment, the method further includes heating the metal-containing layer, the semiconductor layer, and the substrate after plating the metal-containing layer, the semiconductor layer, and before cooling the metal-containing layer, the semiconductor layer, and the substrate. In yet another embodiment, the method further includes creating a weakened region within the semiconductor layer or the substrate, the semiconductor layer, or both during: cooling the metal- containing layer, the semiconductor layer, and the substrate; heating the metal-containing layer, the semiconductor layer, and the substrate; or heating then cooling the metal-containing layer, the semiconductor layer, and the substrate.

In a further embodiment of the third aspect, wherein separating the at least a portion of the semiconductor layer includes fracturing the semiconductor layer at a depth corresponding to a thickness of the at least a portion of the semiconductor layer. In a particular embodiment, separating the at least a portion of the semiconductor layer is performed without using a mechanical separating tool. In still a further embodiment, separating the at least a portion of the semiconductor layer includes cleaving the at least a portion of the semiconductor layer at a depth corresponding to a thickness of the at least a portion of the semiconductor layer. In yet a further embodiment, separating the at least a portion of the semiconductor layer is performed using a wedge, a wire, a saw, a laser, an acoustical device, or any combination thereof. In another embodiment, separating the at least a portion of the semiconductor layer includes applying a metallic paste over the metal-containing layer, attaching a handling substrate, pulling the handling substrate from the substrate such that the at least a portion of the semiconductor layer and the metal-containing layer remain attached to the handling substrate, and removing the at least a portion of the semiconductor layer and the metal-containing layer from the handling substrate. The method further includes forming an electrode electrically connected to the at least a portion of the semiconductor layer to form a free-standing photovoltaic device. In a fourth aspect, a method of forming an electronic device can include forming a semiconductor layer directly contacting a surface of a substrate, wherein at the surface, the substrate has a semiconductor composition that includes silicon, and the semiconductor layer has a semiconductor composition that includes silicon and is at least part of a homojunction portion. The method can further include forming a heterojunction portion after forming the semiconductor layer, forming a metal-containing layer over the heterojunction portion, and separating the homojunction portion, the heterojunction portion, and the metal-containing layer from the substrate.

In an embodiment of the fourth aspect, the method further includes forming an electrode electrically connected to the homojunction portion, wherein the electrode is formed after separating the homojunction portion from the substrate. In a particular embodiment, forming the electrode includes forming a principal conductor that is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm. In another particular embodiment, the principal conductor is in a form of a grid. In still another particular embodiment, forming the electrode further includes a conductive layer over substantially all of the semiconductor before forming the principal conductor, wherein the conductive layer is substantially transparent to the radiation. In a more particular embodiment, the conductive layer includes a layer of indium-tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof. In another more particular embodiment, the principal conductor has a pattern defining openings through which sunlight may be transmitted to the homojunction portion.

In another embodiment of the fourth aspect, the substrate, the semiconductor layer, and the heterojunction portion have substantially a same semiconductor composition. In a more particular embodiment, the semiconductor composition of the substrate, the semiconductor composition of the semiconductor layer, and the semiconductor material include only one or more Group 14 elements. In an even more particular embodiment, the semiconductor composition of the substrate, the semiconductor composition of the semiconductor layer, and the semiconductor material include solely silicon.

In still another embodiment of the fourth aspect, after separating the homojunction portion, the heterojunction portion, and the metal-containing layer from the substrate, a combination of the separating the homojunction portion, the heterojunction portion, and the metal-containing layer is curved. In a particular embodiment, the combination has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is at least approximately 1: 1, at least approximately 2: 1, or at least approximately 4: 1. In another particular embodiment, the combination has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1. In still another particular embodiment, the combination has concave surface and a convex surface opposite the concave surface. In an even more particular embodiment, as compared to the homojunction portion, the metal-containing layer is disposed closer to the concave surface; and as compared to the metal- containing layer, the homojunction portion is disposed closer to the convex surface.

In a further embodiment of the fourth aspect, the method further includes bending or flexing a combination of the separating the homojunction portion, the heterojunction portion, and the metal-containing layer. In still a further embodiment, the method further includes shaping a combination of the separating the homojunction portion, the heterojunction portion, and the metal-containing layer to form to a non-planar surface. In yet a further embodiment, the semiconductor layer has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns. In another embodiment, the semiconductor layer has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns. In still another embodiment, the metal-containing layer has a thickness of at least approximately 11 microns, at least approximately 30 microns, or at least approximately 50 microns. In yet another embodiment, the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than approximately 200 microns.

In another embodiment of the fourth aspect, the method further includes forming a doped region within the semiconductor layer, wherein the doped region has a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³. In a particular embodiment, forming the doped region includes diffusing dopant from the substrate. In another particular embodiment, forming the doped region includes epitaxially growing a first portion of the semiconductor layer from the substrate. In a more particular embodiment, forming the semiconductor layer further includes epitaxially growing a second portion of the semiconductor layer, wherein the second portion is undoped or has a lower dopant concentration than the first portion of semiconductor layer or is substantially undoped. In still another embodiment of the fourth aspect, the method further includes modifying a topology of the heterojunction portion before forming the metal-containing layer. In a particular embodiment, modifying the topology includes wet etching the exposed surface. In a more particular embodiment, wet etching is performed using a basic solution, a colloidal metal solution, or any combination thereof. In another particular embodiment, modifying the topology includes dry etching the exposed surface. In a more particular embodiment, dry etching is performed using a reactive ion etch, a sputter etch, or any combination thereof. In still another particular embodiment, modifying the topology includes mechanically removing a portion of the substrate at the exposed surface. In a more particular embodiment, mechanical removing includes cutting groove or a pattern into a material at the exposed surface, abrading the exposes surface, or any combination thereof.

In yet another embodiment of the fourth aspect, forming the metal-containing layer includes plating a conductive film including 100 %, or at least 99%, or at least 95%, or at least 90% of a total thickness of the metal-containing layer. In a more particular embodiment, forming the metal-containing layer further includes forming an adhesion film, a barrier film, a seed film, or any combination thereof, before plating the conductive film. In a further embodiment, the method further includes cooling the substrate, the semiconductor layer, the heterojunction portion, and the metal-containing layer before separating the homojunction portion, the heterojunction portion, and the metal-containing layer. In another further embodiment, the method further includes heating the substrate, the semiconductor layer, the heterojunction portion, and the metal- containing layer after forming the metal-containing layer. In still a further embodiment, the method further includes creating a weakened region within the semiconductor layer or the substrate during: cooling the substrate, the semiconductor layer, the heterojunction portion, and the metal-containing layer; heating the substrate, the semiconductor layer, the heterojunction portion, and the metal-containing layer; or heating then cooling the substrate, the semiconductor layer, the heterojunction portion, and the metal-containing layer.

In another embodiment of the fourth aspect, separating the homojunction portion, the heterojunction portion, and the metal-containing layer from the substrate includes fracturing the semiconductor layer at a depth corresponding to a thickness of the homojunction portion. In a particular embodiment, separating is performed without using a mechanical separating tool. In still another embodiment, separating the homojunction portion, the heterojunction portion, and the metal-containing layer from the substrate includes cleaving the semiconductor layer at a depth corresponding to a thickness of the homojunction portion. In a particular embodiment, separating is performed using a wedge, a wire, a saw, a laser, an acoustical device, or any combination thereof. In yet another embodiment, separating the homojunction portion, the heterojunction portion, and the metal-containing layer from the substrate includes applying a metallic paste over the metal-containing layer, attaching a handling substrate, pulling the handling substrate from the substrate such that the homojunction portion, the heterojunction portion, and the metal-containing layer remain attached to the handling substrate, and removing the homojunction portion, the heterojunction portion from the handling substrate. The method further includes forming an electrode electrically connected to the homojunction portion to form a free-standing photovoltaic device.

In a further embodiment of the fourth aspect, forming heterojunction portion includes forming another semiconductor layer over the semiconductor layer that includes the homojunction portion, wherein a heterojunction is formed between the semiconductor layers. In another further embodiment, the homojunction and heterojunction portions have a same semiconductor material. In a particular embodiment, forming the heterojunction portion includes depositing a layer of an amorphous semiconductor material, a polycrystalline semiconductor material, or a combination of thereof, and the homojunction portion is substantially monocrystalline. In another particular embodiment, wherein semiconductor compositions of the homojunction and heterojunction portions include only one or more Group 14 elements. In still another particular embodiment, a semiconductor compositions of the homojunction and heterojunction portions include solely silicon. In yet another particular embodiment, the heterojunction portion has a higher energy bandgap as compared to the semiconductor layer. In a further particular embodiment of the fourth aspect, the heterojunction portion has a thickness of at least approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm. In another further particular embodiment, the heterojunction portion has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm. In still a further particular embodiment, forming the heterojunction portion includes chemical vapor deposition technique or physical vapor deposition technique. In a more particular embodiment, chemical vapor depositing includes plasma-enhanced chemical vapor deposition, remote plasma chemical vapor deposition, hot wire chemical vapor deposition, low pressure chemical vapor deposition, atmospheric chemical vapor deposition, or any combination thereof. In another particular embodiment, forming the heterojunction portion includes forming an undoped semiconductor layer. In a more particular embodiment, forming the heterojunction portion further includes forming a doped semiconductor layer over the undoped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of a doped region within the homojunction portion.

In a fifth aspect, a method of forming an electronic device including a photovoltaic device can includes plating a metal-containing layer over the point electrical connections and a substrate including a semiconductor layer. The method can further include separating at least a part of the semiconductor layer and the metal-containing layer from the substrate, wherein after separating, a combination of the at least a portion of the semiconductor layer and the metal-containing layer is curved. In an embodiment of the fifth aspect, the combination has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is at least approximately 1: 1, at least approximately 2: 1, or at least approximately 4: 1. In another embodiment, the combination has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1. In still another embodiment, the combination has concave surface and a convex surface opposite the concave surface. In a more particular embodiment, as compared to the portion of the semiconductor layer, the metal-containing layer is disposed closer to the concave surface; and as compared to the metal-containing layer, the portion of the semiconductor layer is disposed closer to the convex surface.

In a further embodiment of the fifth aspect, the method further includes mounting the combination to a workpiece holder, wherein, while the combination is mounted, the combination is less curved as compared to before mounting; and forming another layer over the combination while the combination is mounted. In a particular embodiment, the workpiece holder includes a coating that including a fluoropolymer, a silicon nitride, a silicon carbide, anodized aluminum. In another particular embodiment, the semiconductor layer has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns. In still another particular embodiment, the semiconductor layer has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

In a further particular embodiment of the fifth aspect, forming the other layer includes forming an electrode adjacent to the semiconductor layer. In a more particular embodiment, forming the electrode includes forming a principal conductor over the at least a portion of the semiconductor layer, wherein the principal conductor is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm. In a more particular embodiment, the principal conductor is in the form of a grid. In another more particular embodiment, the forming electrode further includes forming a conductive layer that is substantially transparent to the radiation, wherein forming the conductive layer is performed before forming the principal conductor. In an even more particular embodiment, the conductive layer includes indium-tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof along a surface of the homojunction portion.

In a sixth aspect, a method of forming an electronic device can include forming a freestanding photovoltaic device that includes a semiconductor layer and a metal-containing layer, wherein the free-standing photovoltaic device is capable of being flexed, bent, shaped, or any combination thereof and remain operational after being flexed, bent, shaped, or any combination thereof.

In an embodiment of the sixth aspect, the method further includes coupling the freestanding photovoltaic device to a corresponding surface of the electronic device. In a particular embodiment, coupling includes removably coupling the free-standing photovoltaic device to the corresponding surface of the electronic device. In another particular embodiment, coupling includes permanently coupling the free-standing photovoltaic device to the corresponding surface of the electronic device. In still another particular embodiment, coupling includes coupling the free-standing photovoltaic device such that it directly contacts the corresponding surface of the electronic device. In yet another particular embodiment, coupling included coupling the freestanding photovoltaic device such that another layer is disposed between the free-standing photovoltaic device the corresponding surface of the electronic device. In a more particular embodiment, the other layer includes an adhesive material. In another more particular embodiment, the other layer includes an interposer including z-axis conductors. In a further particular embodiment of the sixth aspect, coupling includes securing or attaching the free-standing photovoltaic device to the corresponding surface of the electronic device. In another further particular embodiment, the method further includes bending, flexing, or shaping the free-standing photovoltaic device before or during coupling the free-standing photovoltaic device to the corresponding surface of the electronic device. In still a further particular embodiment, the surface of the electronic device where the free-standing photovoltaic device is coupled is non-planar. In a more particular embodiment, the surface is curved, is irregular, or includes a corner or a ridge. In still another particular embodiment, the method further includes shaping the free-standing photovoltaic device to match more closely the corresponding surface of the electronic device. In a more particular embodiment, the free- standing photovoltaic device has a major surface that is closest to the corresponding surface of the electronic device, wherein shaping is performed such that the substantially all of the major surface of the free-standing photovoltaic device matches the corresponding surface of the electronic device. Note that not all of the activities described above in the general description or the examples are required, that a portion of a specific activity may not be required, and that one or more further activities may be performed in addition to those described. Still further, the order in which activities are listed is not necessarily the order in which they are performed. Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims. The specification and illustrations of the embodiments described herein are intended to provide a general understanding of the structure of the various embodiments. The specification and illustrations are not intended to serve as an exhaustive and comprehensive description of all of the elements and features of apparatus and systems that use the structures or methods described herein. Separate embodiments may also be provided in combination in a single embodiment, and conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Further, reference to values stated in ranges includes each and every value within that range. Many other embodiments may be apparent to skilled artisans only after reading this specification. Other embodiments may be used and derived from the disclosure, such that a structural substitution, logical substitution, or another change may be made without departing from the scope of the disclosure. Accordingly, the disclosure is to be regarded as illustrative rather than restrictive.

Claims

WHAT IS CLAIMED IS:

1. An electronic device comprising a photovoltaic device, wherein the photovoltaic device

comprises:

a heterojunction portion having a semiconductor composition that includes silicon; and a homojunction portion having a semiconductor composition that includes silicon,

wherein:

the homojunction portion directly contacts the heterojunction portion at a

heterojunction; and

the heterojunction portion has a higher energy bandgap as compared to the

homojunction portion.

2. The electronic device of claim 1, wherein the homojunction portion comprises a layer having a substantially monocrystalline structure.

3. The electronic device of claim 2, wherein the heterojunction portion is amorphous,

polycrystalline, or a combination of thereof.

4. The electronic device of claim 2, wherein the homojunction portion and the heterojunction portion have substantially a same semiconductor composition.

5. The electronic device of claim 2, wherein the semiconductor composition of the heterojunction portion and the semiconductor composition of the homojunction portion include only one or more Group 14 elements.

6. The electronic device of claim 1, wherein the semiconductor composition of the heterojunction portion and the semiconductor composition of the homojunction portion include solely silicon.

7. The electronic device of claim 1, wherein the heterojunction portion has a thickness of at least approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm.

8. The electronic device of claim 1, wherein the heterojunction portion has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm.

9. The electronic device of claim 1, wherein the heteroj unction portion comprises a plurality of layers.

10. The electronic device of claim 9, wherein the heterojunction portion comprises an undoped semiconductor layer.

11. The electronic device of claim 10, wherein the heterojunction portion further comprises a doped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of the homojunction portion.

12. The electronic device of claim 11, wherein the homojunction portion comprises:

a first doped region having a doping concentration no greater than approximately l lO¹⁸ atoms/cm³, wherein the heterojunction is at the junction of the undoped semiconductor layer and the first doped region; and

a second doped region spaced apart from the heterojunction portion and having a doping concentration of at least approximately lxlO¹⁹ atoms/cm³.

13. The electronic device of claim 11, wherein:

the homojunction portion comprises an n-type substantially monocrystalline

semiconductor layer;

the doped semiconductor layer comprises a p-type semiconductor layer;

the heterojunction is at a junction of the n-type substantially monocrystalline

semiconductor layer and the undoped semiconductor layer; and

the undoped semiconductor layer is an only layer disposed between the n-type

substantially monocrystalline semiconductor layer and the p-type semiconductor layer.

14. The electronic device of claim 1, wherein the homojunction portion has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns.

15. The electronic device of claim 1, wherein the homojunction portion has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

16. The electronic device of claim 1, wherein the photovoltaic device further comprises an

electrode electrically connected to the homojunction portion.

17. The electronic device of claim 16, wherein the electrode comprises a principal conductor that is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm.

18. The electronic device of claim 17, wherein the principal conductor is in a form of a grid.

19. The electronic device of claim 17, wherein the electrode further comprises a conductive layer that is substantially transparent to the radiation.

20. The electronic device of claim 19, wherein the conductive layer comprises indium-tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof.

21. The electronic device of claim 19, wherein the conductive layer is disposed between the principal conductor and the homojunction portion.

22. The electronic device of claim 1, further comprising a metal-containing layer electrically connected to the heterojunction region, wherein the metal-containing layer contacts substantially all of a surface of the heterojunction region.

23. The electronic device of claim 22, wherein the metal-containing layer has a thickness of at least approximately 11 microns, at least approximately 30 microns, or at least

approximately 50 microns.

24. The electronic device of claim 22, wherein the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than approximately 200 microns.

25. The electronic device of claim 22, wherein the metal containing layer comprises a conductive film comprising 100 %, at least 99%, at least 95%, or at least 90% of a total thickness of the metal-containing layer.

26. The electronic device of claim 25, wherein the metal-containing layer further comprises an adhesion film, a barrier film, a seed film, or any combination thereof.

27. The electronic device of claim 22, wherein the heterojunction portion has a surface with a varying topology.

28. The electronic device of claim 27, wherein the metal-containing layer is disposed along the surface with the varying topology.

29. The electronic device of claim 1, wherein the photovoltaic device is a free-standing

photovoltaic device that is curved.

30. The electronic device of claim 29, wherein the photovoltaic device has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is at least approximately 1 : 1, at least approximately 2: 1, or at least approximately 4: 1.

31. The electronic device of claim 29, wherein the photovoltaic device has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1.

32. The electronic device of claim 29, wherein the photovoltaic device has concave surface and a convex surface opposite the concave surface.

33. The electronic device of claim 32, wherein:

as compared to the heterojunction portion, the homojunction portion is disposed closer to the concave surface; and

as compared to the homojunction portion, the heterojunction portion is disposed closer to the convex surface.

34. An electronic device comprising a photovoltaic device, wherein the photovoltaic device comprises:

a semiconductor layer; and

a metal-containing layer electrically connected to the semiconductor layer,

wherein a combination of the semiconductor layer and the metal-containing layer is part of a free-standing photovoltaic device that is curved.

35. The electronic device of claim 34, wherein the photovoltaic device has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is at least approximately 1 : 1, at least approximately 2: 1, or at least approximately 4: 1.

36. The electronic device of claim 34, wherein the photovoltaic device has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1.

37. The electronic device of claim 34, wherein the photovoltaic device has concave surface and a convex surface opposite the concave surface.

38. The electronic device of claim 34, wherein:

as compared to the semiconductor layer, the metal-containing layer is disposed closer to the concave surface; and

as compared to the metal-containing layer, the semiconductor layer is disposed closer to the convex surface.

39. The electronic device of claim 34, wherein the free-standing photovoltaic cell is capable of being flexed, bent, shaped, or any combination thereof.

40. The electronic device of claim 34, wherein the metal-containing layer has a thickness of at least approximately 11 microns, at least approximately 30 microns, or at least

approximately 50 microns.

41. The electronic device of claim 34, wherein the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than approximately 200 microns.

42. The electronic device of claim 34, wherein the metal containing layer comprises a conductive film comprising 100 %, at least 99%, at least 95%, or at least 90% of a total thickness of the metal-containing layer.

43. The electronic device of claim 42, wherein the metal-containing layer further comprises an adhesion film, a barrier film, a seed film, or any combination thereof.

44. The electronic device of claim 34, wherein the photovoltaic device further comprises an electrode, wherein, as compared to the metal-containing layer, the electrode is closer to a light-receiving surface of the photovoltaic device.

45. The electronic device of claim 44, wherein the electrode includes a principal conductor that is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm.

46. The electronic device of claim 45, wherein the principal conductor is in a form of a grid.

47. The electronic device of claim 45, wherein the electrode further comprises a conductive layer that is substantially transparent to the radiation.

48. The electronic device of claim 47, wherein the conductive layer is disposed between the principal conductor and the semiconductor layer.

49. The electronic device of claim 48, wherein the conductive layer comprises indium-tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof.

50. The electronic device of claim 34, further comprising a homojunction portion and a

heterojunction portion, wherein:

a heterojunction is formed at an interface between the homojunction and heterojunction portions; and

the homojunction portion includes the semiconductor layer.

51. The electronic device of claim 50, wherein the semiconductor layer has a substantially

monocrystalline structure and a semiconductor composition that includes silicon.

52. The electronic device of claim 51, wherein the heterojunction portion is amorphous,

polycrystalline, or a combination of thereof.

53. The electronic device of claim 51, wherein the heterojunction portion comprises a layer having a semiconductor composition that includes silicon.

54. The electronic device of claim 51, wherein the homojunction portion and the heterojunction portion have substantially a same semiconductor composition.

55. The electronic device of claim 51, wherein the semiconductor composition of the heterojunction portion and the semiconductor composition of the homojunction portion include only one or more Group 14 elements.

56. The electronic device of claim 51, wherein the semiconductor composition of the

heterojunction portion and the semiconductor composition of the homojunction portion include solely silicon.

57. The electronic device of claim 50, wherein the heterojunction portion has a higher energy bandgap as compared to the semiconductor material of the homojunction portion.

58. The electronic device of claim 50, wherein the heterojunction portion has a thickness of at least approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm.

59. The electronic device of claim 50, wherein the heterojunction portion has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm.

60. The electronic device of claim 50, wherein the heterojunction portion comprises a plurality of layers.

61. The electronic device of claim 60, wherein the heterojunction portion comprises an undoped semiconductor layer.

62. The electronic device of claim 61, wherein the heterojunction portion further comprises a doped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of the homojunction portion.

63. The electronic device of claim 62, wherein the homojunction portion comprises:

a first doped region having a doping concentration no greater than approximately lxlO¹⁸ atoms/cm³, wherein the heterojunction is at the junction of the undoped semiconductor layer and the first doped region; and

64. The electronic device of claim 62, wherein: the homojunction portion comprises an n-type substantially monocrystalline semiconductor layer;

the doped semiconductor layer comprises a p-type semiconductor layer;

the heteroj unction is at a junction of the n-type substantially monocrystalline

semiconductor layer and the undoped semiconductor layer; and

the undoped semiconductor layer is an only layer disposed between the n-type

65. The electronic device of claim 50, wherein the homojunction portion comprises a doped region having a dopant concentration of at least approximately l lO¹⁹ atoms/cm³.

66. The electronic device of claim 50, wherein the homojunction portion has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns.

67. The electronic device of claim 50, wherein the homojunction portion has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

68. A method of forming an electronic device comprising a photovoltaic device, wherein the method comprises:

forming a semiconductor layer directly contacting a surface of a substrate, wherein, at the surface, the substrate includes a semiconductor material;

forming a metal-containing layer over the semiconductor layer; and

separating at least a portion of the semiconductor layer and the metal-containing layer from the substrate, wherein substantially none of the substrate is removed with the semiconductor layer and the metal layer.

69. The method of claim 68, wherein the semiconductor layer and the semiconductor material have substantially a same semiconductor composition.

70. The method of claim 69, wherein the semiconductor compositions of the semiconductor layer and the semiconductor material include only one or more Group 14 elements.

71. The method of claim 70, wherein the semiconductor compositions of the semiconductor layer and the semiconductor material include solely silicon.

72. The method of claim 68, wherein each of the semiconductor layer and the semiconductor material has a substantially monocrystalline structure and a semiconductor composition that includes silicon.

73. The method of claim 68, wherein the at least a portion of the semiconductor layer has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns.

74. The method of claim 68, wherein the at least a portion of semiconductor layer has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

75. The method of claim 68, wherein the metal-containing layer has a thickness of at least

approximately 11 microns, at least approximately 30 microns, or at least approximately 50 microns.

76. The method of claim 68, wherein the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than

approximately 200 microns.

77. The method of claim 68, wherein forming the metal containing layer comprises plating a conductive film comprising 100 %, or at least 99%, or at least 95%, or at least 90% of a total thickness of the metal-containing layer.

78. The method of claim 77, wherein forming the metal-containing layer further comprises forming an adhesion film, a barrier film, a seed film, or any combination thereof, before plating the conductive film.

79. The method of claim 68, further comprising forming a heterojunction portion before forming the metal-containing layer, wherein:

a homojunction portion includes the semiconductor layer; and

a heterojunction lies at an interface between the homojunction portion and the

heterojunction portion.

80. The method of claim 79, wherein the homojunction portion comprises the semiconductor layer having a substantially monocrystalline structure and a semiconductor composition that includes silicon.

81. The method of claim 80, wherein the heterojunction portion is deposited as an amorphous layer or a polycrystalline layer.

82. The method of claim 80, wherein the homojunction portion and the heterojunction portion have substantially a same semiconductor composition.

83. The method of claim 80, wherein the semiconductor composition of the heterojunction

portion and the semiconductor composition of the homojunction portion include only one or more Group 14 elements.

84. The method of claim 80, wherein the semiconductor composition of the heterojunction

portion and the semiconductor composition of the homojunction portion include solely silicon.

85. The method of claim 79, wherein the heterojunction portion has a higher energy bandgap as compared to the homojunction portion.

86. The method of claim 79, wherein the heterojunction portion comprises forming a plurality of layers.

87. The method of claim 86, wherein forming the heterojunction portion comprises forming an undoped semiconductor layer.

88. The method of claim 87, wherein forming the heterojunction portion further comprises

forming a doped semiconductor layer over the undoped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of the first semiconductor layer.

89. The method of claim 79, wherein the heterojunction portion has a thickness of at least

approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm.

90. The method of claim 79, wherein the heterojunction portion has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm.

91. The method of claim 79, wherein forming the heterojunction portion is performed using a chemical vapor deposition technique or a physical vapor deposition technique.

92. The method of claim 91, wherein chemical vapor depositing comprises plasma-enhanced chemical vapor deposition, remote plasma chemical vapor deposition, hot wire chemical vapor deposition, low pressure chemical vapor deposition, atmospheric chemical vapor deposition, or any combination thereof.

93. The method of claim 79, further comprising forming an electrode adjacent to the at least a portion of the semiconductor layer.

94. The method of claim 93, wherein forming the electrode comprises forming a principal

conductor over the at least a portion of the semiconductor layer, wherein the principal conductor is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm.

95. The method of claim 94, wherein the principal conductor is in the form of a grid.

96. The method of claim 94, wherein forming electrode further comprises forming a conductive layer that is substantially transparent to the radiation, wherein forming the conductive layer is performed before forming the principal conductor.

97. The method of claim 96, wherein the conductive layer comprises indium-tin-oxide,

aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof along a surface of the homojunction portion.

98. The method of claim 68, further comprising modifying a topology of an exposed surface at or adjacent to the heterojunction portion before plating the metal-containing layer.

99. The method of claim 98, wherein modifying the topology comprises wet etching the exposed surface.

100. The method of claim 99, wherein wet etching is performed using a basic solution, a colloidal metal solution, or any combination thereof.

101. The method of claim 98, wherein modifying the topology comprises dry etching the exposed surface.

102. The method of claim 101, wherein dry etching is performed using a reactive ion etch, a sputter etch, or any combination thereof.

103. The method of claim 98, wherein modifying the topology comprises mechanically removing a portion of the substrate at the exposed surface.

104. The method of claim 103, wherein mechanical removing comprises cutting groove or a pattern into a material at the exposed surface, abrading the exposes surface, or any combination thereof.

105. The method of claim 68, further comprising forming a doped region within the

semiconductor layer, wherein the doped region has a dopant concentration of at least approximately lxlO¹⁹ atoms/cm³.

106. The method of claim 105, wherein forming the doped region comprises diffusing dopant from the substrate.

107. The method of claim 105, wherein forming the doped region comprises epitaxially growing a first portion of the semiconductor layer from the substrate.

108. The method of claim 107, wherein forming the semiconductor layer further comprises

epitaxially growing a second portion of the semiconductor layer, wherein the second portion is undoped or has a lower dopant concentration than the first portion of semiconductor layer or is substantially undoped.

109. The method of claim 68, further comprising cooling the metal-containing layer, the

semiconductor layer, and the substrate after forming the metal-containing layer and before separating the at least a portion of the semiconductor layer.

110. The method of claim 109, further comprising heating the metal-containing layer, the

semiconductor layer, and the substrate after plating the metal-containing layer, the semiconductor layer, and before cooling the metal-containing layer, the semiconductor layer, and the substrate.

111. The method of claim 68, further comprising creating a weakened region within the

semiconductor layer or the substrate, the semiconductor layer, or both during:

cooling the metal-containing layer, the semiconductor layer, and the substrate;

heating the metal-containing layer, the semiconductor layer, and the substrate; or heating then cooling the metal-containing layer, the semiconductor layer, and the

substrate.

112. The method of claim 68, wherein separating the at least a portion of the semiconductor layer comprises fracturing the semiconductor layer at a depth corresponding to a thickness of the at least a portion of the semiconductor layer.

113. The method of claim 112, wherein separating the at least a portion of the semiconductor layer is performed without using a mechanical separating tool.

114. The method of claim 68, wherein separating the at least a portion of the semiconductor layer comprises cleaving the at least a portion of the semiconductor layer at a depth

corresponding to a thickness of the at least a portion of the semiconductor layer.

115. The method of claim 68, wherein separating the at least a portion of the semiconductor layer is performed using a wedge, a wire, a saw, a laser, an acoustical device, or any combination thereof.

116. The method of claim 68, wherein:

separating the at least a portion of the semiconductor layer comprises:

applying a metallic paste over the metal-containing layer;

attaching a handling substrate;

pulling the handling substrate from the substrate such that the at least a portion of the semiconductor layer and the metal-containing layer remain attached to the handling substrate; and

removing the at least a portion of the semiconductor layer and the metal- containing layer from the handling substrate; and

the process further comprises forming an electrode electrically connected to the at least a portion of the semiconductor layer to form a free-standing photovoltaic device.

117. A method of forming an electronic device comprising:

forming a semiconductor layer directly contacting a surface of a substrate, wherein: at the surface, the substrate has a semiconductor composition that includes silicon; and

the semiconductor layer has a semiconductor composition that includes silicon and is at least part of a homojunction portion;

forming a he teroj unction portion after forming the semiconductor layer;

forming a metal-containing layer over the heterojunction portion; and

separating the homojunction portion, the heterojunction portion, and the metal-containing layer from the substrate.

118. The method of claim 117, further comprising forming an electrode electrically connected to the homojunction portion, wherein the electrode is formed after separating the homojunction portion from the substrate.

119. The method of claim 118, wherein forming the electrode includes forming a principal conductor that is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm.

120. The method of claim 118, wherein the principal conductor is in a form of a grid.

121. The method of claim 118, wherein forming the electrode further comprises a conductive layer over substantially all of the semiconductor before forming the principal conductor, wherein the conductive layer is substantially transparent to the radiation.

122. The method of claim 121, wherein conductive layer comprises a layer of indium-tin-oxide, aluminum-tin-oxide, zinc oxide, a conductive polymer, gold, silver, copper, nickel, or any combination thereof.

123. The method of claim 121, wherein the principal conductor has a pattern defining openings through which sunlight may be transmitted to the homojunction portion.

124. The method of claim 117, wherein the substrate, the semiconductor layer, and the

heterojunction portion have substantially a same semiconductor composition.

125. The method of claim 124, wherein the semiconductor composition of the substrate, the semiconductor composition of the semiconductor layer, and the semiconductor material include only one or more Group 14 elements.

126. The method of claim 125, wherein the semiconductor composition of the substrate, the semiconductor composition of the semiconductor layer, and the semiconductor material include solely silicon.

127. The method of claim 117, wherein after separating the homojunction portion, the

heterojunction portion, and the metal-containing layer from the substrate, a combination of the separating the homojunction portion, the heterojunction portion, and the metal- containing layer is curved.

128. The method of claim 127, wherein the combination has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is at least approximately 1 : 1, at least approximately 2: 1, or at least approximately 4: 1.

129. The method of claim 127, wherein the combination has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1.

130. The method of claim 127, wherein the combination has concave surface and a convex

surface opposite the concave surface.

131. The method of claim 130, wherein:

as compared to the homojunction portion, the metal-containing layer is disposed closer to the concave surface; and

as compared to the metal-containing layer, the homojunction portion is disposed closer to the convex surface.

132. The method of claim 117, further comprising bending or flexing a combination of the

separating the homojunction portion, the heterojunction portion, and the metal-containing layer.

133. The method of claim 117, further comprising shaping a combination of the separating the homojunction portion, the he teroj unction portion, and the metal-containing layer to form to a non-planar surface.

134. The method of claim 117, wherein the semiconductor layer has a thickness of at least approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns.

135. The method of claim 117, wherein the semiconductor layer has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

136. The method of claim 117, wherein the metal-containing layer has a thickness of at least approximately 11 microns, at least approximately 30 microns, or at least approximately 50 microns.

137. The method of claim 117, wherein the metal-containing layer has a thickness no greater than approximately 2 mm, no greater than approximately 1 mm, or no greater than

approximately 200 microns.

138. The method of claim 117, further comprising forming a doped region within the

139. The method of claim 138, wherein forming the doped region comprises diffusing dopant from the substrate.

140. The method of claim 138, wherein forming the doped region comprises epitaxially growing a first portion of the semiconductor layer from the substrate.

141. The method of claim 140, wherein forming the semiconductor layer further comprises epitaxially growing a second portion of the semiconductor layer, wherein the second portion is undoped or has a lower dopant concentration than the first portion of semiconductor layer or is substantially undoped.

142. The method of claim 117, further comprising modifying a topology of the heterojunction portion before forming the metal-containing layer.

143. The method of claim 142, wherein modifying the topology comprises wet etching the exposed surface.

144. The method of claim 143, wherein wet etching is performed using a basic solution, a

colloidal metal solution, or any combination thereof.

145. The method of claim 142, wherein modifying the topology comprises dry etching the

exposed surface.

146. The method of claim 145, wherein dry etching is performed using a reactive ion etch, a sputter etch, or any combination thereof.

147. The method of claim 142, wherein modifying the topology comprises mechanically

removing a portion of the substrate at the exposed surface.

148. The method of claim 147, wherein mechanical removing comprises cutting groove or a pattern into a material at the exposed surface, abrading the exposes surface, or any combination thereof.

149. The method of claim 117, wherein forming the metal-containing layer comprises plating a conductive film comprising 100 %, or at least 99%, or at least 95%, or at least 90% of a total thickness of the metal-containing layer.

150. The method of claim 149, wherein forming the metal-containing layer further comprises forming an adhesion film, a barrier film, a seed film, or any combination thereof, before plating the conductive film.

151. The method of claim 117, further comprising cooling the substrate, the semiconductor layer, the heterojunction portion, and the metal-containing layer before separating the homojunction portion, the heterojunction portion, and the metal-containing layer.

152. The method of claim 117, further comprising heating the substrate, the semiconductor layer, the heterojunction portion, and the metal-containing layer after forming the metal- containing layer.

153. The method of claim 117, further comprising creating a weakened region within the semiconductor layer or the substrate during:

cooling the substrate, the semiconductor layer, the heterojunction portion, and the metal- containing layer;

heating the substrate, the semiconductor layer, the heterojunction portion, and the metal- containing layer; or

heating then cooling the substrate, the semiconductor layer, the heterojunction portion, and the metal-containing layer.

154. The method of claim 117, wherein separating the homojunction portion, the heterojunction portion, and the metal-containing layer from the substrate comprises fracturing the semiconductor layer at a depth corresponding to a thickness of the homojunction portion.

155. The method of claim 154, wherein separating is performed without using a mechanical separating tool.

156. The method of claim 117, wherein separating the homojunction portion, the heterojunction portion, and the metal-containing layer from the substrate comprises cleaving the semiconductor layer at a depth corresponding to a thickness of the homojunction portion.

157. The method of claim 156, wherein separating is performed using a wedge, a wire, a saw, a laser, an acoustical device, or any combination thereof.

158. The method of claim 117, wherein:

separating the homojunction portion, the heterojunction portion, and the metal-containing layer from the substrate comprises:

applying a metallic paste over the metal-containing layer;

attaching a handling substrate;

pulling the handling substrate from the substrate such that the homojunction portion, the heterojunction portion, and the metal-containing layer remain attached to the handling substrate; and

removing the homojunction portion, the heterojunction portion from the handling substrate, and

the process further comprises forming an electrode electrically connected to the

homojunction portion to form a free-standing photovoltaic device.

159. The method of claim 117, wherein forming heterojunction portion comprises forming another semiconductor layer over the semiconductor layer that includes the homojunction portion, wherein a heterojunction is formed between the semiconductor layers.

160. The method of claim 117, wherein the homojunction and heterojunction portions have a same semiconductor material.

161. The method of claim 160, wherein forming the heterojunction portion comprises depositing a layer of an amorphous semiconductor material, a polycrystalline semiconductor material, or a combination of thereof, and the homojunction portion is substantially monocrystalline.

162. The method of claim 160, wherein semiconductor compositions of the homojunction and heterojunction portions include only one or more Group 14 elements.

163. The method of claim 160, wherein semiconductor compositions of the homojunction and heterojunction portions include solely silicon.

164. The method of claim 160, wherein the heterojunction portion has a higher energy bandgap as compared to the semiconductor layer.

165. The method of claim 160, wherein the heterojunction portion has a thickness of at least approximately 3 nm, at least approximately 5 nm, or at least approximately 7 nm.

166. The method of claim 160, wherein the heterojunction portion has a thickness no greater than approximately 60 nm, no greater than approximately 50 nm, or no greater than approximately 40 nm.

167. The method of claim 160, wherein forming the heterojunction portion comprises chemical vapor deposition technique or physical vapor deposition technique.

168. The method of claim 167, wherein chemical vapor depositing comprises plasma-enhanced chemical vapor deposition, remote plasma chemical vapor deposition, hot wire chemical vapor deposition, low pressure chemical vapor deposition, atmospheric chemical vapor deposition, or any combination thereof.

169. The method of claim 160, wherein forming the heterojunction portion comprises forming an undoped semiconductor layer.

170. The method of claim 169, wherein forming the heterojunction portion further comprising forming a doped semiconductor layer over the undoped semiconductor layer, wherein the doped semiconductor layer has a conductivity type opposite that of a doped region within the homojunction portion.

171. A method of forming an electronic device comprising a photovoltaic device, wherein the method comprises:

plating a metal-containing layer over the point electrical connections and a substrate including a semiconductor layer; and

separating at least a part of the semiconductor layer and the metal-containing layer from the substrate, wherein after separating, a combination of the at least a portion of the semiconductor layer and the metal-containing layer is curved.

172. The method of claim 171, wherein the combination has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is at least approximately 1 : 1, at least approximately 2: 1, or at least approximately 4: 1.

173. The method of claim 171, wherein the combination has a lateral dimension and a vertical displacement associated with a curve, wherein a ratio of the lateral dimension to the vertical displacement is no greater than approximately 40: 1, no greater than approximately 20: 1, or no greater than approximately 10: 1.

174. The method of claim 171, wherein the combination has concave surface and a convex

surface opposite the concave surface.

175. The method of claim 174, wherein:

as compared to the portion of the semiconductor layer, the metal-containing layer is disposed closer to the concave surface; and

as compared to the metal-containing layer, the portion of the semiconductor layer is disposed closer to the convex surface.

176. The method of claim 171, further comprising:

mounting the combination to a workpiece holder, wherein, while the combination is mounted, the combination is less curved as compared to before mounting; and forming another layer over the combination while the combination is mounted.

177. The method of claim 176, wherein the workpiece holder comprises a coating that including a fluoropolymer, a silicon nitride, a silicon carbide, anodized aluminum.

178. The method of claim 176, wherein the semiconductor layer has a thickness of at least

approximately 2 microns, at least approximately 11 microns, at least approximately 16 microns, or at least approximately 20 microns.

179. The method of claim 176, wherein the semiconductor layer has a thickness no greater than approximately 90 microns, no greater than approximately 50 microns, no greater than approximately 40 microns, or no greater than approximately 30 microns.

180. The method of claim 176, wherein forming the other layer comprises forming an electrode adjacent to the semiconductor layer.

181. The method of claim 180, wherein forming the electrode comprises forming a principal conductor over the at least a portion of the semiconductor layer, wherein the principal conductor is substantially opaque to radiation at wavelengths in a range of approximately 250 nm to approximately 700 nm.

182. The method of claim 181, wherein the principal conductor is in the form of a grid.

183. The method of claim 181, wherein the forming electrode further comprises forming a

conductive layer that is substantially transparent to the radiation, wherein forming the conductive layer is performed before forming the principal conductor.

184. The method of claim 183, wherein the conductive layer comprises indium-tin-oxide,

185. A method of forming an electronic device comprising forming a free-standing photovoltaic device that includes a semiconductor layer and a metal-containing layer, wherein the freestanding photovoltaic device is capable of being flexed, bent, shaped, or any combination thereof and remain operational after being flexed, bent, shaped, or any combination thereof.

186. The method of claim 185, further comprising coupling the free-standing photovoltaic device to a corresponding surface of the electronic device.

187. The method of claim 186, wherein coupling comprises removably coupling the freestanding photovoltaic device to the corresponding surface of the electronic device.

188. The method of claim 186, wherein coupling comprises permanently coupling the freestanding photovoltaic device to the corresponding surface of the electronic device.

189. The method of claim 186, wherein coupling comprises coupling the free-standing

photovoltaic device such that it directly contacts the corresponding surface of the electronic device.

190. The method of claim 186, wherein coupling comprised coupling the free-standing

photovoltaic device such that another layer is disposed between the free-standing photovoltaic device the corresponding surface of the electronic device.

191. The method of claim 190, wherein the other layer comprises an adhesive material.

192. The method of claim 190, wherein the other layer comprises an interposer including z-axis conductors.

193. The method of claim 186, wherein coupling comprises securing or attaching the freestanding photovoltaic device to the corresponding surface of the electronic device.

194. The method of claim 186, further comprising bending, flexing, or shaping the free-standing photovoltaic device before or during coupling the free-standing photovoltaic device to the corresponding surface of the electronic device.

195. The method of claim 186, wherein the surface of the electronic device where the freestanding photovoltaic device is coupled is non-planar.

196. The method of claim 195, wherein the surface is curved.

197. The method of claim 195, wherein the surface is irregular.

198. The method of claim 195, wherein the surface comprises a corner or a ridge.

199. The method of claim 186, further comprising shaping the free-standing photovoltaic device to match more closely the corresponding surface of the electronic device.

200. The method of claim 199, wherein the free-standing photovoltaic device has a major surface that is closest to the corresponding surface of the electronic device, wherein shaping is performed such that the substantially all of the major surface of the free-standing photovoltaic device matches the corresponding surface of the electronic device.