WO2013095559A1 - Power conservation by way of memory channel shutdown - Google Patents
Power conservation by way of memory channel shutdown Download PDFInfo
- Publication number
- WO2013095559A1 WO2013095559A1 PCT/US2011/067007 US2011067007W WO2013095559A1 WO 2013095559 A1 WO2013095559 A1 WO 2013095559A1 US 2011067007 W US2011067007 W US 2011067007W WO 2013095559 A1 WO2013095559 A1 WO 2013095559A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- dram
- cache lines
- channel
- memory channel
- Prior art date
Links
- 230000015654 memory Effects 0.000 title claims abstract description 365
- 238000000034 method Methods 0.000 claims abstract description 41
- 230000004044 response Effects 0.000 claims abstract description 12
- 238000013519 translation Methods 0.000 claims description 20
- 230000014616 translation Effects 0.000 claims description 20
- 238000012545 processing Methods 0.000 claims description 3
- 229920000682 polycarbomethylsilane Polymers 0.000 claims 15
- 230000003213 activating effect Effects 0.000 claims 1
- 108091006146 Channels Proteins 0.000 description 124
- 230000005291 magnetic effect Effects 0.000 description 12
- 230000005012 migration Effects 0.000 description 12
- 238000013508 migration Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- 235000019580 granularity Nutrition 0.000 description 9
- 238000007726 management method Methods 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 230000002085 persistent effect Effects 0.000 description 6
- 238000013459 approach Methods 0.000 description 5
- 210000004027 cell Anatomy 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000005192 partition Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- JWZQBEUBJXSDPP-UHFFFAOYSA-N 5-cyclohexyl-6-methylpyrimidine-2,4-diamine Chemical compound CC1=NC(N)=NC(N)=C1C1CCCCC1 JWZQBEUBJXSDPP-UHFFFAOYSA-N 0.000 description 2
- 101100072002 Arabidopsis thaliana ICME gene Proteins 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 210000004271 bone marrow stromal cell Anatomy 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000005387 chalcogenide glass Substances 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000012217 deletion Methods 0.000 description 2
- 230000037430 deletion Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- -1 poly(N-vinylcarbazole) Polymers 0.000 description 2
- 238000000638 solvent extraction Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 150000004770 chalcogenides Chemical class 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005294 ferromagnetic effect Effects 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- CGIGDMFJXJATDK-UHFFFAOYSA-N indomethacin Chemical compound CC1=C(CC(O)=O)C2=CC(OC)=CC=C2N1C(=O)C1=CC=C(Cl)C=C1 CGIGDMFJXJATDK-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229920003227 poly(N-vinyl carbazole) Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000007420 reactivation Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3275—Power saving in memory, e.g. RAM, cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1028—Power efficiency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1041—Resource optimization
- G06F2212/1044—Space efficiency improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/202—Non-volatile memory
- G06F2212/2024—Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/205—Hybrid memory, e.g. using both volatile and non-volatile memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- This invention relates generally to the field of computer systems. More particularly, the invention relates to an apparatus and method for implementing a multi-level memory hierarchy.
- system memory also known as main memory, primary memory, executable memory
- DRAM dynamic random access memory
- main memory main memory
- primary memory executable memory
- DRAM-based memory consumes power even when no memory reads or writes occur because it must constantly recharge internal capacitors.
- DRAM-based memory is volatile, which means data stored in DRAM memory is lost once the power is removed.
- a cache is a high speed memory positioned between the processor and system memory to service memory access requests faster than they could be serviced from system memory.
- Such caches are typically implemented with static random access memory (SRAM).
- SRAM static random access memory
- Cache management protocols may be used to ensure that the most frequently accessed data and instructions are stored within one of the levels of cache, thereby reducing the number of memory access transactions and improving performance.
- mass storage also known as secondary storage or disk storage
- conventional mass storage devices typically include magnetic media (e.g., hard disk drives), optical media (e.g., compact disc (CD) drive, digital versatile disc (DVD), etc.), holographic media, and/or mass-storage flash memory (e.g., solid state drives (SSDs), removable flash drives, etc.).
- these storage devices are considered Input/Output (I/O) devices because they are accessed by the processor through various I/O adapters that implement various I/O protocols.
- I/O adapters and I/O protocols consume a significant amount of power and can have a significant impact on the die area and the form factor of the platform.
- Portable or mobile devices e.g., laptops, netbooks, tablet computers, personal digital assistant (PDAs), portable media players, portable gaming devices, digital cameras, mobile phones, smartphones, feature phones, etc.
- PDAs personal digital assistant
- portable media players portable gaming devices
- digital cameras mobile phones, smartphones, feature phones, etc.
- removable mass storage devices e.g., Embedded Multimedia Card (eMMC), Secure Digital (SD) card
- eMMC Embedded Multimedia Card
- SD Secure Digital
- BIOS flash With respect to firmware memory (such as boot memory (also known as BIOS flash)), a conventional computer system typically uses flash memory devices to store persistent system information that is read often but seldom (or never) written to. For example, the initial instructions executed by a processor to initialize key system components during a boot process (Basic Input and Output System (BIOS) images) are typically stored in a flash memory device. Flash memory devices that are currently available in the market generally have limited speed (e.g., 50 MHz). This speed is further reduced by the overhead for read protocols (e.g., 2.5 MHz). In order to speed up the BIOS execution speed, conventional processors generally cache a portion of BIOS code during the Pre-Extensible Firmware Interface (PEI) phase of the boot process. The size of the processor cache places a restriction on the size of the BIOS code used in the PEI phase (also known as the "PEI BIOS code").
- PEI Pre-Extensible Firmware Interface
- PCM Phase-Change Memory
- Phase-change memory also sometimes referred to as phase change random access memory (PRAM or PCRAM), PCME, Ovonic Unified Memory, or Chalcogenide RAM (C- RAM)
- PCM Phase-change memory
- PCME phase change random access memory
- C- RAM Chalcogenide RAM
- FIGURE 1 illustrates a cache and system memory arrangement according to embodiments of the invention
- FIGURE 2 illustrates a memory and storage hierarchy employed in embodiments of the invention
- FIGURE 3 shows a memory computing system having a DRAM section of system memory and a PCMS section of system memory;
- FIGURE 4 shows a methodology for shutting down a memory channel;
- FIGURE 5 shows a methodology for re-activating a memory channel
- FIGURE 6 shows memory power state table for use by a power management system
- FIGURE 7 shows components for implementing shutdown/reactivation of a memory channel.
- references in the specification to "one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
- Coupled is used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, co-operate or interact with each other.
- Connected is used to indicate the establishment of communication between two or more elements that are coupled with each other.
- Bracketed text and blocks with dashed borders are sometimes used herein to illustrate optional operations/components that add additional features to embodiments of the invention. However, such notation should not be taken to mean that these are the only options or optional operations/components, and/or that blocks with solid borders are not optional in certain embodiments of the invention.
- NVRAM non-volatile random access memory
- NVRAM in the memory hierarchy also enables new usages such as expanded boot space and mass storage implementations, as described in detail below.
- FIGURE 1 illustrates a cache and system memory arrangement according to embodiments of the invention.
- Figure 1 shows a memory hierarchy including a set of internal processor caches 120, "near memory” acting as a far memory cache 121, which may include both internal cache(s) 106 and external caches 107-109, and "far memory” 122.
- One particular type of memory which may be used for "far memory” in some embodiments of the invention is non- volatile random access memory (“NVRAM”).
- NVRAM non- volatile random access memory
- NVRAM NVRAM
- PCM Phase Change Memory and Switch
- BPRAM byte-addressable persistent memory
- PMC programmable metallization cell
- RRAM resistive memory
- RESET amorphous cell
- ferroelectric memory also known as polymer memory and poly(N-vinylcarbazole)
- ferromagnetic memory also known as Spintronics
- SPRAM spin-transfer torque RAM
- STRAM spin tunneling RAM
- magnetoresistive memory magnetic memory
- MRAM magnetic random access memory
- SONOS Semiconductor-oxide- nitride-oxide-semiconductor
- NVRAM has the following characteristics:
- the bus may be a memory bus (e.g., a DDR bus such as DDR3, DDR4, etc.) over which is run a transactional protocol as opposed to the non-transactional protocol that is normally used.
- a transactional protocol a protocol that supports transaction identifiers (IDs) to distinguish different transactions so that those transactions can complete out-of-order
- the bus may be a memory bus (e.g., a DDR bus such as DDR3, DDR4, etc.) over which is run a transactional protocol as opposed to the non-transactional protocol that is normally used.
- the bus may one over which is normally run a transactional protocol (a native transactional protocol), such as a PCI express (PCIE) bus, desktop management interface (DMI) bus, or any other type of bus utilizing a transactional protocol and a small enough transaction payload size (e.g., cache line size such as 64 or 128 byte); and (7) one or more of the following: a) faster write speed than non- volatile memory/storage technologies such as FLASH; b) very high read speed (faster than FLASH and near or equivalent to DRAM read speeds); c) directly writable (rather than requiring erasing (overwriting with Is) before writing data like FLASH memory used in SSDs); and/or d) orders of magnitude (e.g., 2 or 3) higher write endurance before failure (more than boot ROM and FLASH used in SSDs).
- a native transactional protocol such as a PCI express (PCIE) bus, desktop management interface (DMI) bus, or any other type of bus utilizing a transactional
- the level of granularity at which NVRAM is accessed in any given implementation may depend on the particular memory controller and the particular memory bus or other type of bus to which the NVRAM is coupled.
- the NVRAM may be accessed at the granularity of a cache line (e.g., a 64-byte or 128-Byte cache line), notwithstanding an inherent ability to be accessed at the granularity of a byte, because cache line is the level at which the memory subsystem accesses memory.
- NVRAM when NVRAM is deployed within a memory subsystem, it may be accessed at the same level of granularity as the DRAM (e.g., the "near memory") used in the same memory subsystem. Even so, the level of granularity of access to the NVRAM by the memory controller and memory bus or other type of bus is smaller than that of the block size used by Flash and the access size of the I/O subsystem's controller and bus.
- NVRAM may also incorporate wear leveling algorithms to account for the fact that the storage cells at the far memory level begin to wear out after a number of write accesses, especially where a significant number of writes may occur such as in a system memory implementation. Since high cycle count blocks are most likely to wear out in this manner, wear leveling spreads writes across the far memory cells by swapping addresses of high cycle count blocks with low cycle count blocks. Note that most address swapping is typically transparent to application programs because it is handled by hardware, lower-level software (e.g., a low level driver or operating system), or a combination of the two.
- lower-level software e.g., a low level driver or operating system
- the far memory 122 of some embodiments of the invention is implemented with NVRAM, but is not necessarily limited to any particular memory technology. Far memory 122 is distinguishable from other instruction and data memory/storage technologies in terms of its characteristics and/or its application in the memory/storage hierarchy.
- far memory 122 is different from: static random access memory (SRAM) which may be used for level 0 and level 1 internal processor caches lOla-b, 102a-b, 103a-b, 103a-b, and 104a-b dedicated to each of the processor cores 101-104, respectively, and lower level cache (LLC) 105 shared by the processor cores; dynamic random access memory (DRAM) configured as a cache 106 internal to the processor 100 (e.g., on the same die as the processor 100) and/or configured as one or more caches 107-109 external to the processor (e.g., in the same or a different package from the processor 100); and
- SRAM static random access memory
- DRAM dynamic random access memory
- FLASH memory/magnetic disk/optical disc applied as mass storage (not shown); and memory such as FLASH memory or other read only memory (ROM) applied as firmware memory (which can refer to boot ROM, BIOS Flash, and/or TPM Flash). (not shown).
- ROM read only memory
- Far memory 122 may be used as instruction and data storage that is directly addressable by a processor 100 and is able to sufficiently keep pace with the processor 100 in contrast to FLASH/magnetic disk/optical disc applied as mass storage. Moreover, as discussed above and described in detail below, far memory 122 may be placed on a memory bus and may
- Far memory 122 may be combined with other instruction and data storage technologies (e.g., DRAM) to form hybrid memories (also known as Co-locating PCM and DRAM; first level memory and second level memory; FLAM (FLASH and DRAM)).
- DRAM instruction and data storage technologies
- hybrid memories also known as Co-locating PCM and DRAM; first level memory and second level memory; FLAM (FLASH and DRAM)
- PCM/PCMS may be used for mass storage instead of, or in addition to, system memory, and need not be random accessible, byte addressable or directly addressable by the processor when applied in this manner.
- NVRAM non-volatile memory
- PCM PCM
- PCMS PCMS
- far memory may be used interchangeably in the following discussion. However it should be realized, as discussed above, that different technologies may also be utilized for far memory. Also, that NVRAM is not limited for use as far memory.
- FIG. 1 illustrates how various levels of caches 101-109 are configured with respect to a system physical address (SPA) space 116-119 in embodiments of the invention.
- this embodiment comprises a processor 100 having one or more cores 101-104, with each core having its own dedicated upper level cache (LO) 10 la- 104a and mid- level cache (MLC) (LI) cache 101b-104b.
- the processor 100 also includes a shared LLC 105. The operation of these various cache levels are well understood and will not be described in detail here.
- the caches 107-109 illustrated in Figure 1 may be dedicated to a particular system memory address range or a set of non-contiguous address ranges.
- cache 107 is dedicated to acting as a Memory Side Cache (MSC) for system memory address range # 1 116 and caches 108 and 109 are dedicated to acting as MSCs for non-overlapping portions of system memory address ranges # 2 117 and # 3 118.
- MSC Memory Side Cache
- the latter implementation may be used for systems in which the SPA space used by the processor 100 is interleaved into an address space used by the caches 107-109 (e.g., when configured as MSCs). In some embodiments, this latter address space is referred to as a memory channel address (MCA) space.
- MCA memory channel address
- the internal caches 10 la- 106 perform caching operations for the entire SPA space.
- System memory as used herein is memory which is visible to and/or directly addressable by software executed on the processor 100; while the cache memories 101a-109 may operate transparently to the software in the sense that they do not form a directly- addressable portion of the system address space, but the cores may also support execution of instructions to allow software to provide some control (configuration, policies, hints, etc.) to some or all of the cache(s).
- the subdivision of system memory into regions 116-119 may be performed manually as part of a system configuration process (e.g., by a system designer) and/or may be performed automatically by software.
- system memory regions 116-119 are implemented using far memory (e.g., PCM) and, in some embodiments, near memory configured as system memory.
- System memory address range # 4 represents an address range which is implemented using a higher speed memory such as DRAM which may be a near memory configured in a system memory mode (as opposed to a caching mode).
- FIG. 2 illustrates a memory/storage hierarchy 140 and different configurable modes of operation for near memory 144 and NVRAM according to embodiments of the invention.
- the memory/storage hierarchy 140 has multiple levels including (1) a cache level 150 which may include processor caches 150A (e.g., caches 101A-105 in Figure 1) and optionally near memory as cache for far memory 150B (in certain modes of operation), (2) a system memory level 151 which includes far memory 15 IB (e.g., NVRAM such as PCM) and near memory operating as system memory 151 A, (3) a mass storage level 152 which may include a flash/magnetic/optical mass storage 152B and/or NVRAM mass storage 152A (e.g., a portion of the NVRAM 142); and (4) a firmware memory level 153 that may include BIOS flash 170 and/or BIOS NVRAM 172 and optionally trusted platform module (TPM) NVRAM 173.
- a cache level 150 which may include processor caches 150A (e.g
- near memory 144 may be implemented to operate in a mode in which it operates as system memory 151 A and occupies a portion of the SPA space (sometimes referred to as near memory "direct access" mode); and one or more additional modes of operation such as a scratchpad memory 192 or as a write buffer 193.
- the near memory is partitionable, where each partition may concurrently operate in a different one of the supported modes; and different embodiments may support configuration of the partitions (e.g., sizes, modes) by hardware (e.g., fuses, pins), firmware, and/or software (e.g., through a set of programmable range registers within the MSC controller 124 within which, for example, may be stored different binary codes to identify each mode and partition).
- system address space B 191 is used to show an implementation when all or a portion of near memory is assigned a portion of the system address space.
- system address space B 191 represents the range of the system address space assigned to the near memory 151A and system address space A 190 represents the range of the system address space assigned to NVRAM 174.
- NUMA non-uniform memory address
- HPC high performance computing
- graphics applications which require very fast access to certain data structures.
- Figure 2 also illustrates that a portion of the NVRAM 142 may be used as firmware memory.
- the BIOS NVRAM 172 portion may be used to store BIOS images (instead of or in addition to storing the BIOS information in BIOS flash 170).
- the BIOS NVRAM portion 172 may be a portion of the SPA space and is directly addressable by software executed on the processor cores 101-104, whereas the BIOS flash 170 is addressable through the I/O subsystem 115.
- a trusted platform module (TPM) NVRAM 173 portion may be used to protect sensitive system information (e.g., encryption keys).
- TPM trusted platform module
- the NVRAM 142 may be implemented to operate in a variety of different modes, including as far memory 15 IB (e.g., when near memory 144 is
- NVRAM mass storage 152A NVRAM mass storage 152A
- BIOS NVRAM 172 BIOS NVRAM 172
- TPM NVRAM 173 TPM NVRAM 173.
- system memory and mass storage devices may depend on the type of electronic platforms on which embodiments of the invention are employed.
- the mass storage may be implemented using NVRAM mass storage 152A alone, or using NVRAM mass storage 152A in combination with a flash/magnetic/optical mass storage 152B.
- the mass storage may be implemented using magnetic storage (e.g., hard drives) or any combination of magnetic storage, optical storage, holographic storage, mass- storage flash memory, and NVRAM mass storage 152A.
- system hardware and/or software responsible for storage may implement various intelligent persistent storage allocation techniques to allocate blocks of persistent program code and data between the FM
- a high powered server is configured with a near memory (e.g., DRAM), a PCMS device, and a magnetic mass storage device for large amounts of persistent storage.
- a notebook computer is configured with a near memory and a PCMS device which performs the role of both a far memory and a mass storage device.
- a home or office desktop computer is configured similarly to a notebook computer, but may also include one or more magnetic storage devices to provide large amounts of persistent storage capabilities.
- a tablet computer or cellular telephony device is configured with PCMS memory but potentially no near memory and no additional mass storage (for cost/power savings).
- the tablet/telephone may be configured with a removable mass storage device such as a flash or PCMS memory stick.
- portable media players and/or personal digital assistants may be configured in a manner similar to tablets/telephones described above, gaming consoles may be configured in a similar manner to desktops or laptops.
- Other devices which may be similarly configured include digital cameras, routers, set-top boxes, digital video recorders, televisions, and automobiles.
- Figure 3 shows a memory controller 300 of a computing system having respective interfaces 301_1 to 301_8 to a plurality of memory channels (e.g., DDR channels) 302_1 to 302_8 where each channel is capable of supporting one or more DIMM cards (that is, one or more DIMM cards can be plugged into the channel), and, Figures 4 and 5 show methods for controlling the power consumption of a computing system by disabling/enabling a memory channel and its corresponding DIMM cards. For simplicity eight memory channels are shown but those of ordinary skill will understand that the teachings herein can be applied to systems having differing numbers of memory channels.
- DDR channels e.g., DDR channels
- a decision may be made (e.g., by intelligent power management software such as ACPI) to enter a computer system into a lower performance state by disabling a memory channel that is presently operative.
- a decision may be made to enter the computer system into a higher performance state by enabling a memory channel that is presently inoperative.
- NVRAM system memory components may reserve a first portion of system memory addresses for DRAM, and, a second portion of system memory addresses for NVRAM. That is, in the "near memory acting as system memory approach", addressable system memory can include both DRAM (see, e.g., Figure 2, near memory as system memory 151 A) and PCMS (see, e.g., Figure 2 far memory 15 IB implemented as NVRAM system memory 174).
- DRAM see, e.g., Figure 2, near memory as system memory 151 A
- PCMS see, e.g., Figure 2 far memory 15 IB implemented as NVRAM system memory 174.
- each of the memory channels 302_1 to 302_8 is allotted a unique portion or segment of the computer's system memory addresses consistent with the storage space available on the memory channel.
- the storage space available on a memory channel is a function of the number of DIMM cards plugged into the memory channel, and, the storage density of the memory devices on the DIMM cards.
- a first portion 303 of the memory channels (and therefore a corresponding first portion/segment of the system memory address space) is reserved for DRAM DIMMs, and, a second portion 304 of the memory channels (and therefore a corresponding, remaining second portion/segment of the system memory address space) is reserved for PCMS DIMMs.
- the DRAM storage space 303 does not act as a cache for the PCMS storage space 304. Rather, the system memory space is configured to store "access time critical" information (such as program code instructions, or, at least, frequently utilized program code instructions) in the DRAM storage space 303, and, "not, or less, access time critical” information (such as data, or, at least, infrequently accessed data) in the PCMS storage space 304.
- "access time critical" information such as program code instructions, or, at least, frequently utilized program code instructions
- access time critical information such as data, or, at least, infrequently accessed data
- the operating system and/or virtual machine monitor running on the computer's CPU allocate the system memory address space consistent with this scheme. For example, frequently used program code instructions (at least) are given address space that corresponds to those memory channels having DRAM DIMMs, and, infrequently used data items (at least) are given address space that corresponds to those memory channels having PCMS DIMMs.
- the content stored at each address, whether DRAM or PCMS is a fixed length data word (e.g., a 64 bit data word or a 128 bit data word) referred to as a "cache line".
- a fixed length data word e.g., a 64 bit data word or a 128 bit data word
- the disablement of a memory channel to enter a lower performance state includes disabling the memory channel's DIMM cards and their corresponding memory devices
- the enabling of a memory channel to enter a higher performance state includes enabling the memory channel's DIMM cards and their corresponding memory devices.
- DRAM DIMM cards are chosen to be enabled/disabled.
- DRAM devices are faster and consume more power than PCMS devices
- dropping to a lower performance state by shutting down a DRAM memory channel should significantly lower a computing system's performance and power consumption.
- rising to a higher performance state by enabling a DRAM memory channel should significantly increase the computer system's performance and power consumption.
- Memory management is a matter of concern, however. Specifically, when a DRAM memory channel is disabled or enabled, the system memory address space should be effectively reconfigured to account for the change in available DRAM memory space. This includes "moving" the content of the DRAM channel to be shutdown to other system memory location. According to the methodology of Figure 4, the operating system and/or a virtual machine monitor and/or virtual machine and/or power management component of any of these
- system software keeps track of the usage 402 of virtual addresses that are allocated to DRAM to build an understanding of which virtual addresses are being accessed more frequently and/or which virtual addresses are being accessed less frequently.
- system software is typically designed to refer to virtual addresses and the underlying hardware is responsible for translating the virtual addresses into corresponding physical addresses of the system memory resident in the system.
- the system software When a decision is made to disable a DRAM memory channel, the system software effectively reconfigures the DRAM address space such that more frequently used virtual addresses remain assigned to DRAM address space, and, a group of lesser used DRAM virtual addresses, approximately or identically equal in number to the physical addresses kept by the DRAM memory channel that is to be shut down, are re-assigned to PCMS address space.
- the resulting reassignment of underlying physical addresses necessarily affects the virtual address to physical address translations referred to just above.
- a translation lookaside buffer (TLB) 305 resident in the central processing unit (CPU) or "processor” 306 acts as a cache of virtual address to physical address translations.
- TLB translation lookaside buffer
- a TLB is well understood in the art, but a brief overview of its role and function is worthy of mention.
- a TLB contains a number of translation entries (TEs), each TE identifying a unique physical address for a specific virtual address, also referred to as an address translation.
- a virtual address's TE contains the psychical address of its corresponding memory page in the computing system's system memory.
- the TLB is designed to contain the set of TEs (up to the size of the TLB) whose associated virtual addresses were most recently called out by the executing program code.
- various processor architectures may include both an instruction TLB and a data TLB.
- a next virtual address for a next instruction is fetched and a lookup is performed in the instruction TLB for a match between the virtual address of the instruction and the virtual addresses within the instruction TLB TEs.
- the lookup parameter i.e., higher ordered bits of the virtual address
- the physical address found in the TE having the matching virtual address identifies a specific memory page in system memory where the desired instruction can be found. If a matching virtual address is not found in the instruction TLB (an instruction TLB
- tablewalk hardware of the processor fetches the appropriate TE from system memory.
- the physical address within the TE fetched from system memory identifies the memory page in system memory where the next instruction can be found.
- a copy of the TE fetched from system memory is also typically loaded in the instruction TLB and a least recently used TE is evicted from the instruction TLB. The original TE fetched from system memory remains in system memory.
- the data TLB including system operation in response to a data TLB miss operates much the same as described above except that the virtual address is for a desired data item and the physical address found in the desired TE identifies a page in system memory where the desired data is found.
- the set of TEs containing all virtual address to physical address translations (for both instruction and data) for the set of virtual addresses that an operational program (e.g., an application and/or a virtual machine) may call out over the course of its operation are located in a special store 307, referred to as a "TE store", that is kept in system memory.
- a TE store for an operational program is loaded into system memory as part of the loading of the operational program into memory for execution.
- a TE store is kept in system memory for each operational program.
- all TE stores, and therefore all TEs are kept in a special segment of DRAM system memory on an DRAM channel that cannot be disabled.
- the aforementioned movement of the DRAM memory content creates a need, for each cache line that is to be migrated and therefore have a "new" physical address, to update its corresponding TE to reflect its new physical address location 404.
- the specific TEs that should be updated include: i) TEs of more frequently used DRAM addresses whose content is to be migrated from a DRAM channel being shutdown to a DRAM channel that is not being shutdown; and, ii) TEs of less frequently used DRAM addresses whose corresponding content is to be migrated to PCMS address space.
- the number of least frequently used DRAM addresses identified for migration to PCMS storage is the same (or approximately the same as) the number of addresses that are supported by the DRAM channel to be shut down. This essentially corresponds to equating the number of DRAM addresses that are flagged for migration to PCMS storage space with the number of DRAM addresses that are "lost" by way of the shutdown of the DRAM channel.
- an address on another DRAM channel that is to remain active should be the same as the number of least frequently used DRAM addresses on those DRAM channel(s) that are to remain active whose content needs to be migrated to a new PCMS address (i.e., an address in PCMS storage).
- the content of the former can replace the content of the later in the DRAM space that is to remain active after the channel shutdown. That is, the content of frequently used DRAM addresses on the DRAM channel being shutdown can be written into the DRAM addresses of the least frequently used DRAM addresses of the DRAM channel(s) that are not being shutdown.
- the cache lines of least frequently used DRAM addresses are read from DRAM and written into PCMS storage space 403.
- the physical address information for their respective memory pages as kept in their corresponding TEs (in their respective TE stores - because multiple software applications may be affected by the channel shutdown) in system memory are modified to reflect their new respective PCMS addresses 404.
- the "just vacated" DRAM addresses on the active DRAM channels are re-populated with the cache lines of the frequently used DRAM addresses on the DRAM channel that is to be shutdown 405.
- each vacated least frequently used DRAM address on a remaining active channel is rewritten with a cache line from another more frequently used DRAM address on the channel that is to be shutdown.
- the TE record in system memory for each of the memory pages of the more frequently used DRAM addresses being migrated from the channel that is to be shutdown to the remaining active DRAM channel(s) is modified to reflect its new physical address location
- each new physical address corresponds to an address that was previously identified as being least frequently used.
- a section of PCMS storage 308 is reserved for receiving "a DRAM channel's worth" of cache lines in case of a DRAM channel shutdown.
- no active information is stored in the PCMS section unless and until a DRAM channel is shutdown, at which point, a number of cache lines equivalent in total data size to the storage capacity of the DRAM channel being shutdown is loaded into the section 308 from the DRAM storage space.
- these cache lines are subsequently accessed from the PCMS section to support program operation.
- Multiple such sections of PCMS system memory may be pre-reserved as described above to support a system that can operate while multiple DRAM channels are shutdown 407.
- any copy of a modified TE resident in a TLB is invalidated. Note that system operation may be suspended over the course of the system memory configuration as well.
- a subsequent decision may be made by system software to enter a higher performance state 502 which includes the activation of a presently inactive DRAM channel 502.
- a higher performance state 502 which includes the activation of a presently inactive DRAM channel 502.
- aforementioned section 308 of PCMS system memory 304 reserved for storage of content migrated down from DRAM are "re-migrated back up" to the DRAM channel being activated 503.
- the physical address component of the TEs for the corresponding memory pages of all such cache lines are modified in the TE store 307 to reflect their new storage in the newly activated DRAM channel 504. Again, system operation may be suspended to implement the DRAM channel activation, cache line migration, TE modification and invalidation of any copies of modified TEs resident in a TLB.
- Figure 6 shows a software table structure hierarchy that may be utilized, for example, by intelligent power management software (such as ACPI) to support the ability of a computer system to enable/disable a memory channel as described above.
- the memory power state table 600 hierarchy includes a header 601, a set of commands 602, definitions of one or more power nodes 603_1 to 603_X, and the characteristics of the different power states 604_1 to 604_Y supported by the region of system memory represented by the memory power state table 600.
- a single instance of a memory power state table may instantiated, for example, for any of: an entire system memory, a technology specific region of a system memory (such as a first table instantiated for a DRAM section of system memory and a second table instantiated for a PCMS section of system memory), etc.
- the header information 601 includes information that is specific to the portion of system memory that the memory power state is instantiated on behalf of.
- the header information 601 includes: i) a signature for the table; ii) the length of the entire table including all of its components 602, 603, 604; iii) the version number of the table's structure; iv) a checksum for the table; v) an OEM identifier; vi) an ID of a vendor of a utility that created the table; and, vii) an ID of a revision of the utility that created the table.
- the set of commands include basic commands for reading/writing information from/to the power state table and its various components.
- the memory power state table identifies the number (X) of power node structures 603 listed in the table and includes, or at least provides references to, the power node structures themselves 603_1 through 603_X.
- a separate power node structure instance is created for each memory channel in the portion of memory that the table 600 represents that is capable of supporting multiple power states - any one of which may be programmably entered. For example, referring briefly to Figure 3, if the memory power state table 600 represents the DRAM portion 303 of a system memory having both DRAM 303 and PCMS 304 sections, a separate power node structure can be instantiated for each DRAM memory channel 302_1 to 302_4.
- each power node structure such as power node structure 603_1, includes: i) an identifier of the power node structure 605; ii) the address range 606 of the system memory address space that the power node structure represents; and, iii) the power state 607 that the specific section of system memory represented by the power node structure 606 is currently in.
- the current memory power state 607 corresponds to one of the power states from the set of memory power states 604_1 to 604_Y defined by the power state table 600 as a whole.
- the address range 606 of the power node structure corresponds to a range of virtual system memory addresses whose translation into physical address space corresponds to physical addresses supported by the channel.
- the aforementioned shutdown and re-enablement of a memory channel can "scramble" a contiguous virtual address range across multiple memory channels. Said another way, at least after a channel shutdown sequence, a single memory channel may support multiple non-contiguous sections of virtual address space. This fragmentation of virtual address space over its corresponding physical storage resources may be compounded each time a memory channel shutdown sequence is initiated.
- multiple additional power node structures 603_1_2 to 603_1_R may be instantiated for the same memory channel, where, each such power node structure instance corresponds to a different range of virtual address space that is effectively stored in the channel.
- the various power node structure instances can be effectively "tied” together in a manner that is representative of their corresponding virtual address ranges being stored on the same memory channel by entering the same power node structure identifier element 605 in each of them. Any action taken to this particular identifier will naturally invoke all of the power node structures 603_1 and 603_1_2 to 603_1_R having the identifier.
- the power node structure instance(s) of a particular memory channel should be modified to reflect the "new" virtual addresses that the channel supports the storage of. This may involve any of: the addition of new or the deletion of existing power node structure instances instantiated for the memory channel, and/or, modification of the virtual address ranges 606 specified in existing power node structure instances instantiated for the memory channel.
- modification of the virtual address ranges 606 specified in existing power node structure instances instantiated for the memory channel when a memory channel is shutdown or re-activated, not only are TE entries in a TE store in system memory modified for affected virtual address to physical address translations, but also, address range 606 elements of power node structures used by power management software, as well as the number of such structures themselves, may also be modified.
- the current power state 607 of the memory channel's power node structure instance(s) corresponds to a low power state in which the memory channel is shutdown and is not actively being used.
- the application of clock, strobing and/or refresh signals to the DIMM cards on the memory channel may be suspended.
- the power supply voltages applied to the DIMM cards on the channel may also be reduced as part of the low power state's set of characteristics.
- the current power state setting 607 of the memory channel's power node structure instance(s) will change to another power state that corresponds to the memory channel being active. In this case, any disabled signals or supply voltages are re-applied.
- driver software embedded in an operating system that is associated with a memory channel can oversee the disabling of the various signals and supply voltages when entering a low power state as well as the enabling of various signals and supply voltages when entering a higher power state.
- the current memory power state setting 607 includes a pointer 610 that points to the specific power state amongst the set of power states 604_1 to 604_Y supported by the table 600 that the power node structure 603_1 is currently in.
- each power state definition amongst the power state definitions 604_1 to 604_Y defines the average power consumed (and/or max - min power consumption rates) when a system memory component is in that power state.
- each power state definition also includes a definition of the amount of time that is expended when transitioning into or out of the power state (e.g., an exit latency).
- FIG. 7 shows a software architecture that includes power management software 710, a power management table 700 as discussed above, and, a component 711 of memory management software 712 that keeps track of the usage rates for a software program's virtual addresses and updates the TE information of migrating cache lines.
- the power management software function 710 (such as ACPI) decides that a lower system power state is necessary. With prior awareness, through the availability of the power
- each of the power nodes 703_1 - 703_N correspond to different DRAM (and possibly PCMS) memory channels resident in the computing system each having multiple DIMM cards plugged into them.
- power node 703_2 corresponds to a DRAM memory channel.
- Memory management software 712 for the underlying memory channels of the computer system is invoked 713 in response to the command 712 and recognizes the specific DRAM memory channel that is to be shutdown.
- the memory management software 712 includes a tracking component 711 that tracks which DRAM allocated virtual addresses are more frequently used and which DRAM allocated virtual addresses are less frequently used. Subtracting the loss of DRAM storage capacity with the shutdown of the DRAM memory channel, a new smaller DRAM capacity for the system is understood. The most frequently used DRAM virtual addresses (and/or other "time access critical virtual addresses are flagged) consistent with this capacity are identified for keeping in DRAM storage. The remainder correspond to a collection of lesser used DRAM virtual addresses, the size of whose corresponding content is equivalent to the capacity of the memory channel to be shutdown.
- a migration control component 714 controls the appropriate cache line migration as discussed above.
- the migration includes reading the cache lines associated with lesser used virtual addresses from DRAM (those on the memory channel to be shut down and those on another DRAM memory channel) and writing them into reserved space in PCMS memory.
- the cache lines associated with frequently used virtual addresses located on the memory channel to be shutdown are migrated into locations of the remaining active memory channels that were effectively vacated by the migration into PCMS memory space.
- the TEs in the TE store of virtual addresses having a new physical address owing to migration are updated 715 and any affected TEs in a TLB are invalidated.
- the address range information of the power nodes in the power table 700 that represent the remaining active DRAM memory channels are then updated 716 to reflect their new virtual address ranges. This may include the creation or deletion of power node instances that are identified as being part of the same power node.
- the power channel is then shutdown, for example, by device driver software 717 for the memory channel that can stop or slow down various clock/strobe signals on the channel (and possibly further reduce a supply voltage on the memory channel).
- the power channel can be reactivated according to a similar flow but where the migration control component 714 migrates the cache lines previously stored in PCMS onto the re-activated memory channel.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Power Sources (AREA)
Abstract
Description
Claims
Priority Applications (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201180076411.3A CN104115132B (en) | 2011-12-22 | 2011-12-22 | The power save closed by means of storage channel |
DE112011106032.7T DE112011106032B4 (en) | 2011-12-22 | 2011-12-22 | Energy saving by memory channel shutdown |
KR1020147017930A KR101572403B1 (en) | 2011-12-22 | 2011-12-22 | Power conservation by way of memory channel shutdown |
KR1020157033114A KR101761044B1 (en) | 2011-12-22 | 2011-12-22 | Power conservation by way of memory channel shutdown |
US13/997,999 US9612649B2 (en) | 2011-12-22 | 2011-12-22 | Method and apparatus to shutdown a memory channel |
PCT/US2011/067007 WO2013095559A1 (en) | 2011-12-22 | 2011-12-22 | Power conservation by way of memory channel shutdown |
GB1411390.6A GB2513748B (en) | 2011-12-22 | 2011-12-22 | Power conservation by way of memory channel shutdown |
BR112014015441-4A BR112014015441B1 (en) | 2011-12-22 | 2011-12-22 | energy conservation through memory channel shutdown |
TW101145912A TWI614752B (en) | 2011-12-22 | 2012-12-06 | Power conservation by way of memory channel shutdown |
US15/477,857 US10521003B2 (en) | 2011-12-22 | 2017-04-03 | Method and apparatus to shutdown a memory channel |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2011/067007 WO2013095559A1 (en) | 2011-12-22 | 2011-12-22 | Power conservation by way of memory channel shutdown |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/997,999 A-371-Of-International US9612649B2 (en) | 2011-12-22 | 2011-12-22 | Method and apparatus to shutdown a memory channel |
US15/477,857 Division US10521003B2 (en) | 2011-12-22 | 2017-04-03 | Method and apparatus to shutdown a memory channel |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013095559A1 true WO2013095559A1 (en) | 2013-06-27 |
Family
ID=48669200
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2011/067007 WO2013095559A1 (en) | 2011-12-22 | 2011-12-22 | Power conservation by way of memory channel shutdown |
Country Status (8)
Country | Link |
---|---|
US (2) | US9612649B2 (en) |
KR (2) | KR101572403B1 (en) |
CN (1) | CN104115132B (en) |
BR (1) | BR112014015441B1 (en) |
DE (1) | DE112011106032B4 (en) |
GB (1) | GB2513748B (en) |
TW (1) | TWI614752B (en) |
WO (1) | WO2013095559A1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016023519A1 (en) * | 2014-08-15 | 2016-02-18 | Mediatek Inc. | Method for managing multi-channel memory device to have improved channel switch response time and related memory control system |
WO2016133682A1 (en) * | 2015-02-20 | 2016-08-25 | Qualcomm Incorporated | Adaptive memory access to local and non-local memories |
EP3060993A1 (en) * | 2013-10-21 | 2016-08-31 | Marvell World Trade Ltd. | Final level cache system and corresponding method |
EP3142015A1 (en) * | 2015-09-09 | 2017-03-15 | MediaTek Inc. | Low-power memory-access method and associated apparatus |
US9858201B2 (en) | 2015-02-20 | 2018-01-02 | Qualcomm Incorporated | Selective translation lookaside buffer search and page fault |
WO2019066689A1 (en) * | 2017-09-27 | 2019-04-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and reallocation component for managing reallocation of information from source to target memory sled |
US11556469B2 (en) | 2018-06-18 | 2023-01-17 | FLC Technology Group, Inc. | Method and apparatus for using a storage system as main memory |
US11822474B2 (en) | 2013-10-21 | 2023-11-21 | Flc Global, Ltd | Storage system and method for accessing same |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8597360B2 (en) | 2004-11-03 | 2013-12-03 | Neuropro Technologies, Inc. | Bone fusion device |
WO2013023098A1 (en) | 2011-08-09 | 2013-02-14 | Neuropro Spinal Jaxx Inc. | Bone fusion device, apparatus and method |
US9507534B2 (en) * | 2011-12-30 | 2016-11-29 | Intel Corporation | Home agent multi-level NVM memory architecture |
US9532883B2 (en) | 2012-04-13 | 2017-01-03 | Neuropro Technologies, Inc. | Bone fusion device |
CA2906531C (en) | 2013-03-15 | 2020-10-06 | Neuropro Technologies, Inc. | Bodiless bone fusion device, apparatus and method |
US9389675B2 (en) * | 2013-12-19 | 2016-07-12 | International Business Machines Corporation | Power management for in-memory computer systems |
KR102314138B1 (en) * | 2015-03-05 | 2021-10-18 | 삼성전자 주식회사 | Mobile Device and Method for Data Managing of Mobile Device |
US10127406B2 (en) * | 2015-03-23 | 2018-11-13 | Intel Corporation | Digital rights management playback glitch avoidance |
CN105117285B (en) * | 2015-09-09 | 2019-03-19 | 重庆大学 | A kind of nonvolatile memory method for optimizing scheduling based on mobile virtual system |
US9990283B2 (en) * | 2015-10-16 | 2018-06-05 | SK Hynix Inc. | Memory system |
US9977604B2 (en) * | 2015-10-16 | 2018-05-22 | SK Hynix Inc. | Memory system |
US9977605B2 (en) * | 2015-10-16 | 2018-05-22 | SK Hynix Inc. | Memory system |
US9990143B2 (en) * | 2015-10-16 | 2018-06-05 | SK Hynix Inc. | Memory system |
US9977606B2 (en) * | 2015-10-16 | 2018-05-22 | SK Hynix Inc. | Memory system |
US9824419B2 (en) * | 2015-11-20 | 2017-11-21 | International Business Machines Corporation | Automatically enabling a read-only cache in a language in which two arrays in two different variables may alias each other |
US10303372B2 (en) | 2015-12-01 | 2019-05-28 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and operation method thereof |
US10387127B2 (en) | 2016-07-19 | 2019-08-20 | Sap Se | Detecting sequential access data and random access data for placement on hybrid main memory for in-memory databases |
US10783146B2 (en) | 2016-07-19 | 2020-09-22 | Sap Se | Join operations in hybrid main memory systems |
US10452539B2 (en) * | 2016-07-19 | 2019-10-22 | Sap Se | Simulator for enterprise-scale simulations on hybrid main memory systems |
US10540098B2 (en) | 2016-07-19 | 2020-01-21 | Sap Se | Workload-aware page management for in-memory databases in hybrid main memory systems |
US10698732B2 (en) | 2016-07-19 | 2020-06-30 | Sap Se | Page ranking in operating system virtual pages in hybrid memory systems |
US10437798B2 (en) | 2016-07-19 | 2019-10-08 | Sap Se | Full system simulator and memory-aware splay tree for in-memory databases in hybrid memory systems |
US10474557B2 (en) | 2016-07-19 | 2019-11-12 | Sap Se | Source code profiling for line-level latency and energy consumption estimation |
US10318428B2 (en) | 2016-09-12 | 2019-06-11 | Microsoft Technology Licensing, Llc | Power aware hash function for cache memory mapping |
US10430085B2 (en) | 2016-11-08 | 2019-10-01 | Micron Technology, Inc. | Memory operations on data |
US10261876B2 (en) | 2016-11-08 | 2019-04-16 | Micron Technology, Inc. | Memory management |
US10111760B2 (en) | 2017-01-18 | 2018-10-30 | Neuropro Technologies, Inc. | Bone fusion system, device and method including a measuring mechanism |
US10729560B2 (en) | 2017-01-18 | 2020-08-04 | Neuropro Technologies, Inc. | Bone fusion system, device and method including an insertion instrument |
US10241561B2 (en) | 2017-06-13 | 2019-03-26 | Microsoft Technology Licensing, Llc | Adaptive power down of intra-chip interconnect |
US11010379B2 (en) | 2017-08-15 | 2021-05-18 | Sap Se | Increasing performance of in-memory databases using re-ordered query execution plans |
CN108632152A (en) * | 2018-03-30 | 2018-10-09 | 上海康斐信息技术有限公司 | A kind of wireless router and the method quickly started |
US11163680B2 (en) | 2018-11-28 | 2021-11-02 | International Business Machines Corporation | Dynamic write-back to non-volatile memory |
US10642734B1 (en) | 2018-12-03 | 2020-05-05 | Advanced Micro Devices, Inc. | Non-power of two memory configuration |
US11307779B2 (en) * | 2019-09-11 | 2022-04-19 | Ceremorphic, Inc. | System and method for flash and RAM allocation for reduced power consumption in a processor |
US11721379B2 (en) | 2021-06-17 | 2023-08-08 | Micron Technology, Inc. | Cell disturb on power state transition |
CN113886291B (en) * | 2021-08-29 | 2023-08-18 | 苏州浪潮智能科技有限公司 | Path disabling method and system |
US20230266899A1 (en) * | 2022-02-23 | 2023-08-24 | Nvidia Corporation | System level hardware mechanisms for dynamic assist control |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7376037B1 (en) * | 2005-09-26 | 2008-05-20 | Lattice Semiconductor Corporation | Programmable logic device with power-saving architecture |
US20080235528A1 (en) * | 2007-03-23 | 2008-09-25 | Sungjoon Kim | Progressive power control of a multi-port memory device |
US20090037641A1 (en) * | 2007-07-31 | 2009-02-05 | Bresniker Kirk M | Memory controller with multi-protocol interface |
US20100162020A1 (en) * | 2008-12-22 | 2010-06-24 | International Business Machines Corporation | Power Management of a Spare DRAM on a Buffered DIMM by Issuing a Power On/Off Command to the DRAM Device |
Family Cites Families (89)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US22008A (en) * | 1858-11-09 | Hoisting-machine | ||
US122011A (en) * | 1871-12-19 | Improvement in keepers for door-latches | ||
US711129A (en) * | 1901-11-18 | 1902-10-14 | Robert Shedenhelm | Animal-shears. |
US711207A (en) * | 1901-12-14 | 1902-10-14 | Martin V Grogan | Circular handsaw. |
US5912839A (en) | 1998-06-23 | 1999-06-15 | Energy Conversion Devices, Inc. | Universal memory element and method of programming same |
US7000102B2 (en) | 2001-06-29 | 2006-02-14 | Intel Corporation | Platform and method for supporting hibernate operations |
US6917999B2 (en) | 2001-06-29 | 2005-07-12 | Intel Corporation | Platform and method for initializing components within hot-plugged nodes |
US6732241B2 (en) * | 2001-09-07 | 2004-05-04 | Hewlett-Packard Development Company, L.P. | Technique for migrating data between storage devices for reduced power consumption |
US7493438B2 (en) | 2001-10-03 | 2009-02-17 | Intel Corporation | Apparatus and method for enumeration of processors during hot-plug of a compute node |
US7117311B1 (en) | 2001-12-19 | 2006-10-03 | Intel Corporation | Hot plug cache coherent interface method and apparatus |
US7673090B2 (en) | 2001-12-19 | 2010-03-02 | Intel Corporation | Hot plug interface control method and apparatus |
US7003658B2 (en) | 2002-02-21 | 2006-02-21 | Inventec Corporation | Method for user setup of memory throttling register in north bridge via BIOS to save power |
US20040028066A1 (en) * | 2002-08-06 | 2004-02-12 | Chris Quanbeck | Receiver architectures with dynamic symbol memory allocation and methods therefor |
TW200410255A (en) | 2002-12-10 | 2004-06-16 | Comax Semiconductor Inc | A memory device with power-saving mode and an electrics device with the memory device |
US7350087B2 (en) | 2003-03-31 | 2008-03-25 | Intel Corporation | System and method of message-based power management |
TW564991U (en) * | 2003-04-25 | 2003-12-01 | Sunplus Technology Co Ltd | Power-saving static memory control circuit |
US7376775B2 (en) | 2003-12-29 | 2008-05-20 | Intel Corporation | Apparatus, system, and method to enable transparent memory hot plug/remove |
US7475174B2 (en) | 2004-03-17 | 2009-01-06 | Super Talent Electronics, Inc. | Flash / phase-change memory in multi-ring topology using serial-link packet interface |
US8046488B2 (en) * | 2004-05-21 | 2011-10-25 | Intel Corporation | Dynamically modulating link width |
US7337368B2 (en) | 2004-06-07 | 2008-02-26 | Dell Products L.P. | System and method for shutdown memory testing |
US7480808B2 (en) * | 2004-07-16 | 2009-01-20 | Ati Technologies Ulc | Method and apparatus for managing power consumption relating to a differential serial communication link |
US7562202B2 (en) * | 2004-07-30 | 2009-07-14 | United Parcel Service Of America, Inc. | Systems, methods, computer readable medium and apparatus for memory management using NVRAM |
US7590918B2 (en) | 2004-09-10 | 2009-09-15 | Ovonyx, Inc. | Using a phase change memory as a high volume memory |
US7246224B2 (en) | 2004-09-27 | 2007-07-17 | Intel Corporation | System and method to enable platform personality migration |
US20070005922A1 (en) | 2005-06-30 | 2007-01-04 | Swaminathan Muthukumar P | Fully buffered DIMM variable read latency |
US8010764B2 (en) * | 2005-07-07 | 2011-08-30 | International Business Machines Corporation | Method and system for decreasing power consumption in memory arrays having usage-driven power management |
TWM286985U (en) * | 2005-08-22 | 2006-02-01 | Regulus Technologies Co Ltd | Memory module with smart-type power-saving and fault-tolerance |
US8145732B2 (en) | 2005-11-21 | 2012-03-27 | Intel Corporation | Live network configuration within a link based computing system |
US7496742B2 (en) * | 2006-02-07 | 2009-02-24 | Dell Products L.P. | Method and system of supporting multi-plugging in X8 and X16 PCI express slots |
US7600078B1 (en) | 2006-03-29 | 2009-10-06 | Intel Corporation | Speculatively performing read transactions |
US7913147B2 (en) | 2006-05-08 | 2011-03-22 | Intel Corporation | Method and apparatus for scrubbing memory |
US7756053B2 (en) | 2006-06-30 | 2010-07-13 | Intel Corporation | Memory agent with error hardware |
US7493439B2 (en) | 2006-08-01 | 2009-02-17 | International Business Machines Corporation | Systems and methods for providing performance monitoring in a memory system |
JP4209906B2 (en) | 2006-08-02 | 2009-01-14 | 株式会社日立製作所 | Low power consumption memory management method and computer using the method |
US8051253B2 (en) | 2006-09-28 | 2011-11-01 | Virident Systems, Inc. | Systems and apparatus with programmable memory control for heterogeneous main memory |
WO2008055270A2 (en) * | 2006-11-04 | 2008-05-08 | Virident Systems, Inc. | Writing to asymmetric memory |
US8344475B2 (en) * | 2006-11-29 | 2013-01-01 | Rambus Inc. | Integrated circuit heating to effect in-situ annealing |
US20080270811A1 (en) | 2007-04-26 | 2008-10-30 | Super Talent Electronics Inc. | Fast Suspend-Resume of Computer Motherboard Using Phase-Change Memory |
US8429493B2 (en) | 2007-05-12 | 2013-04-23 | Apple Inc. | Memory device with internal signap processing unit |
JP2009211153A (en) * | 2008-02-29 | 2009-09-17 | Toshiba Corp | Memory device, information processing apparatus, and electric power controlling method |
US20090313416A1 (en) | 2008-06-16 | 2009-12-17 | George Wayne Nation | Computer main memory incorporating volatile and non-volatile memory |
US8161304B2 (en) * | 2009-01-20 | 2012-04-17 | Microsoft Corporation | Power management for large memory subsystems |
US8331857B2 (en) | 2009-05-13 | 2012-12-11 | Micron Technology, Inc. | Wireless interface to program phase-change memories |
US8250282B2 (en) | 2009-05-14 | 2012-08-21 | Micron Technology, Inc. | PCM memories for storage bus interfaces |
US8180981B2 (en) * | 2009-05-15 | 2012-05-15 | Oracle America, Inc. | Cache coherent support for flash in a memory hierarchy |
US8504759B2 (en) | 2009-05-26 | 2013-08-06 | Micron Technology, Inc. | Method and devices for controlling power loss |
US20100306453A1 (en) | 2009-06-02 | 2010-12-02 | Edward Doller | Method for operating a portion of an executable program in an executable non-volatile memory |
US9123409B2 (en) | 2009-06-11 | 2015-09-01 | Micron Technology, Inc. | Memory device for a hierarchical memory architecture |
KR20100133710A (en) * | 2009-06-12 | 2010-12-22 | 삼성전자주식회사 | Memory system and code data loading method therof |
US20110047316A1 (en) * | 2009-08-19 | 2011-02-24 | Dell Products L.P. | Solid state memory device power optimization |
US8578138B2 (en) | 2009-08-31 | 2013-11-05 | Intel Corporation | Enabling storage of active state in internal storage of processor rather than in SMRAM upon entry to system management mode |
US8296496B2 (en) * | 2009-09-17 | 2012-10-23 | Hewlett-Packard Development Company, L.P. | Main memory with non-volatile memory and DRAM |
US9041720B2 (en) * | 2009-12-18 | 2015-05-26 | Advanced Micro Devices, Inc. | Static image retiling and power management method and circuit |
US8407516B2 (en) | 2009-12-23 | 2013-03-26 | Intel Corporation | Controlling memory redundancy in a system |
US8914568B2 (en) * | 2009-12-23 | 2014-12-16 | Intel Corporation | Hybrid memory architectures |
US20110179311A1 (en) * | 2009-12-31 | 2011-07-21 | Nachimuthu Murugasamy K | Injecting error and/or migrating memory in a computing system |
US8612809B2 (en) | 2009-12-31 | 2013-12-17 | Intel Corporation | Systems, methods, and apparatuses for stacked memory |
US20110161592A1 (en) | 2009-12-31 | 2011-06-30 | Nachimuthu Murugasamy K | Dynamic system reconfiguration |
US8621255B2 (en) * | 2010-02-18 | 2013-12-31 | Broadcom Corporation | System and method for loop timing update of energy efficient physical layer devices using subset communication techniques |
US20110208900A1 (en) | 2010-02-23 | 2011-08-25 | Ocz Technology Group, Inc. | Methods and systems utilizing nonvolatile memory in a computer system main memory |
US9015441B2 (en) * | 2010-04-30 | 2015-04-21 | Microsoft Technology Licensing, Llc | Memory usage scanning |
KR20110131781A (en) | 2010-05-31 | 2011-12-07 | 삼성전자주식회사 | Method for presuming accuracy of location information and apparatus for the same |
US9032398B2 (en) * | 2010-07-12 | 2015-05-12 | Vmware, Inc. | Online classification of memory pages based on activity level represented by one or more bits |
JP2012027655A (en) * | 2010-07-22 | 2012-02-09 | Hitachi Ltd | Information processor and power-saving memory management method |
US8762760B2 (en) * | 2010-09-14 | 2014-06-24 | Xilinx, Inc. | Method and apparatus for adaptive power control in a multi-lane communication channel |
US8838935B2 (en) * | 2010-09-24 | 2014-09-16 | Intel Corporation | Apparatus, method, and system for implementing micro page tables |
US8649212B2 (en) | 2010-09-24 | 2014-02-11 | Intel Corporation | Method, apparatus and system to determine access information for a phase change memory |
US8612676B2 (en) | 2010-12-22 | 2013-12-17 | Intel Corporation | Two-level system main memory |
US8462577B2 (en) | 2011-03-18 | 2013-06-11 | Intel Corporation | Single transistor driver for address lines in a phase change memory and switch (PCMS) array |
US8462537B2 (en) | 2011-03-21 | 2013-06-11 | Intel Corporation | Method and apparatus to reset a phase change memory and switch (PCMS) memory cell |
US8607089B2 (en) | 2011-05-19 | 2013-12-10 | Intel Corporation | Interface for storage device access over memory bus |
US8605531B2 (en) | 2011-06-20 | 2013-12-10 | Intel Corporation | Fast verify for phase change memory with switch |
US8463948B1 (en) | 2011-07-01 | 2013-06-11 | Intel Corporation | Method, apparatus and system for determining an identifier of a volume of memory |
US8671309B2 (en) | 2011-07-01 | 2014-03-11 | Intel Corporation | Mechanism for advanced server machine check recovery and associated system software enhancements |
EP2761464B1 (en) | 2011-09-30 | 2018-10-24 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy having different operating modes |
US9529708B2 (en) * | 2011-09-30 | 2016-12-27 | Intel Corporation | Apparatus for configuring partitions within phase change memory of tablet computer with integrated memory controller emulating mass storage to storage driver based on request from software |
WO2013048485A1 (en) * | 2011-09-30 | 2013-04-04 | Intel Corporation | Autonomous initialization of non-volatile random access memory in a computer system |
CN103946813B (en) * | 2011-09-30 | 2017-08-25 | 英特尔公司 | Generation based on the remote memory access signals followed the trail of using statistic |
EP2761471B1 (en) | 2011-09-30 | 2017-10-25 | Intel Corporation | Statistical wear leveling for non-volatile system memory |
EP2761472B1 (en) * | 2011-09-30 | 2020-04-01 | Intel Corporation | Memory channel that supports near memory and far memory access |
EP2761468B1 (en) | 2011-09-30 | 2019-12-11 | Intel Corporation | Platform storage hierarchy with non-volatile random access memory having configurable partitions |
WO2013048497A1 (en) * | 2011-09-30 | 2013-04-04 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy |
US9430372B2 (en) * | 2011-09-30 | 2016-08-30 | Intel Corporation | Apparatus, method and system that stores bios in non-volatile random access memory |
WO2013048500A1 (en) | 2011-09-30 | 2013-04-04 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy over common memory channels |
US20130091331A1 (en) * | 2011-10-11 | 2013-04-11 | Iulian Moraru | Methods, apparatus, and articles of manufacture to manage memory |
US8593866B2 (en) * | 2011-11-11 | 2013-11-26 | Sandisk Technologies Inc. | Systems and methods for operating multi-bank nonvolatile memory |
US9829951B2 (en) * | 2011-12-13 | 2017-11-28 | Intel Corporation | Enhanced system sleep state support in servers using non-volatile random access memory |
US9336147B2 (en) * | 2012-06-12 | 2016-05-10 | Microsoft Technology Licensing, Llc | Cache and memory allocation for virtual machines |
US9811276B1 (en) * | 2015-09-24 | 2017-11-07 | EMC IP Holding Company LLC | Archiving memory in memory centric architecture |
-
2011
- 2011-12-22 KR KR1020147017930A patent/KR101572403B1/en not_active IP Right Cessation
- 2011-12-22 US US13/997,999 patent/US9612649B2/en active Active
- 2011-12-22 WO PCT/US2011/067007 patent/WO2013095559A1/en active Application Filing
- 2011-12-22 CN CN201180076411.3A patent/CN104115132B/en active Active
- 2011-12-22 DE DE112011106032.7T patent/DE112011106032B4/en active Active
- 2011-12-22 BR BR112014015441-4A patent/BR112014015441B1/en active IP Right Grant
- 2011-12-22 KR KR1020157033114A patent/KR101761044B1/en active IP Right Grant
- 2011-12-22 GB GB1411390.6A patent/GB2513748B/en active Active
-
2012
- 2012-12-06 TW TW101145912A patent/TWI614752B/en active
-
2017
- 2017-04-03 US US15/477,857 patent/US10521003B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7376037B1 (en) * | 2005-09-26 | 2008-05-20 | Lattice Semiconductor Corporation | Programmable logic device with power-saving architecture |
US20080235528A1 (en) * | 2007-03-23 | 2008-09-25 | Sungjoon Kim | Progressive power control of a multi-port memory device |
US20090037641A1 (en) * | 2007-07-31 | 2009-02-05 | Bresniker Kirk M | Memory controller with multi-protocol interface |
US20100162020A1 (en) * | 2008-12-22 | 2010-06-24 | International Business Machines Corporation | Power Management of a Spare DRAM on a Buffered DIMM by Issuing a Power On/Off Command to the DRAM Device |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11360894B2 (en) | 2013-10-21 | 2022-06-14 | Flc Global, Ltd. | Storage system and method for accessing same |
US11822474B2 (en) | 2013-10-21 | 2023-11-21 | Flc Global, Ltd | Storage system and method for accessing same |
EP3060993A1 (en) * | 2013-10-21 | 2016-08-31 | Marvell World Trade Ltd. | Final level cache system and corresponding method |
EP3060993B1 (en) * | 2013-10-21 | 2023-03-08 | FLC Global, Ltd. | Final level cache system and corresponding method |
US10037275B2 (en) | 2014-08-15 | 2018-07-31 | Mediatek Inc. | Method for managing multi-channel memory device to have improved channel switch response time and related memory control system |
US9965384B2 (en) | 2014-08-15 | 2018-05-08 | Mediatek Inc. | Method for managing multi-channel memory device to have improved channel switch response time and related memory control system |
WO2016023519A1 (en) * | 2014-08-15 | 2016-02-18 | Mediatek Inc. | Method for managing multi-channel memory device to have improved channel switch response time and related memory control system |
CN107209721A (en) * | 2015-02-20 | 2017-09-26 | 高通股份有限公司 | Local and non-local memory adaptive memory is accessed |
US9858201B2 (en) | 2015-02-20 | 2018-01-02 | Qualcomm Incorporated | Selective translation lookaside buffer search and page fault |
CN107209721B (en) * | 2015-02-20 | 2020-10-23 | 高通股份有限公司 | Adaptive memory access to local and non-local memory |
US9658793B2 (en) | 2015-02-20 | 2017-05-23 | Qualcomm Incorporated | Adaptive mode translation lookaside buffer search and access fault |
WO2016133682A1 (en) * | 2015-02-20 | 2016-08-25 | Qualcomm Incorporated | Adaptive memory access to local and non-local memories |
EP3142015A1 (en) * | 2015-09-09 | 2017-03-15 | MediaTek Inc. | Low-power memory-access method and associated apparatus |
WO2019066689A1 (en) * | 2017-09-27 | 2019-04-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and reallocation component for managing reallocation of information from source to target memory sled |
US11216203B2 (en) | 2017-09-27 | 2022-01-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and reallocation component for managing reallocation of information from source to target memory sled |
US11556469B2 (en) | 2018-06-18 | 2023-01-17 | FLC Technology Group, Inc. | Method and apparatus for using a storage system as main memory |
US11880305B2 (en) | 2018-06-18 | 2024-01-23 | FLC Technology Group, Inc. | Method and apparatus for using a storage system as main memory |
Also Published As
Publication number | Publication date |
---|---|
CN104115132B (en) | 2018-02-06 |
US9612649B2 (en) | 2017-04-04 |
GB2513748A (en) | 2014-11-05 |
BR112014015441A2 (en) | 2017-06-13 |
US20170206010A1 (en) | 2017-07-20 |
US20140143577A1 (en) | 2014-05-22 |
CN104115132A (en) | 2014-10-22 |
GB2513748B (en) | 2020-08-19 |
BR112014015441A8 (en) | 2017-07-04 |
KR20140098221A (en) | 2014-08-07 |
TWI614752B (en) | 2018-02-11 |
KR101572403B1 (en) | 2015-11-26 |
GB201411390D0 (en) | 2014-08-13 |
KR101761044B1 (en) | 2017-07-24 |
DE112011106032B4 (en) | 2022-06-15 |
US10521003B2 (en) | 2019-12-31 |
DE112011106032T5 (en) | 2014-12-04 |
TW201331941A (en) | 2013-08-01 |
KR20150138404A (en) | 2015-12-09 |
BR112014015441B1 (en) | 2021-05-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10521003B2 (en) | Method and apparatus to shutdown a memory channel | |
US10719443B2 (en) | Apparatus and method for implementing a multi-level memory hierarchy | |
US11054876B2 (en) | Enhanced system sleep state support in servers using non-volatile random access memory | |
US9817758B2 (en) | Instructions to mark beginning and end of non transactional code region requiring write back to persistent storage | |
US10102126B2 (en) | Apparatus and method for implementing a multi-level memory hierarchy having different operating modes | |
US9317429B2 (en) | Apparatus and method for implementing a multi-level memory hierarchy over common memory channels | |
US9286205B2 (en) | Apparatus and method for phase change memory drift management | |
US20140229659A1 (en) | Thin translation for system access of non volatile semicondcutor storage as random access memory | |
US9202548B2 (en) | Efficient PCMS refresh mechanism |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 11878192 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13997999 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112011106032 Country of ref document: DE Ref document number: 1120111060327 Country of ref document: DE |
|
ENP | Entry into the national phase |
Ref document number: 1411390 Country of ref document: GB Kind code of ref document: A Free format text: PCT FILING DATE = 20111222 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1411390.6 Country of ref document: GB |
|
ENP | Entry into the national phase |
Ref document number: 20147017930 Country of ref document: KR Kind code of ref document: A |
|
REG | Reference to national code |
Ref country code: BR Ref legal event code: B01A Ref document number: 112014015441 Country of ref document: BR |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 11878192 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 112014015441 Country of ref document: BR Kind code of ref document: A2 Effective date: 20140623 |