WO2013118415A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2013118415A1 WO2013118415A1 PCT/JP2012/083529 JP2012083529W WO2013118415A1 WO 2013118415 A1 WO2013118415 A1 WO 2013118415A1 JP 2012083529 W JP2012083529 W JP 2012083529W WO 2013118415 A1 WO2013118415 A1 WO 2013118415A1
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- WIPO (PCT)
- Prior art keywords
- conductive
- conductive pattern
- fixed
- insulating substrate
- pin
- Prior art date
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- 239000002184 metal Substances 0.000 claims abstract description 194
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Definitions
- the present invention relates to a semiconductor device such as a semiconductor module.
- FIG. 16 A conventional semiconductor device will be described with reference to a cross-sectional view of relevant parts in FIG.
- the semiconductor device in FIG. 16 is exemplified by a 2-in-1 semiconductor module 500.
- 101 is a metal base plate for heat dissipation.
- Reference numeral 102 denotes an insulating substrate with a conductive pattern (ceramic insulating substrate) mounted on the metal base plate 101 and joined by solder 103.
- the insulating substrate with a conductive pattern (ceramic insulating substrate) 102 is a substrate in which a conductive pattern 102b is bonded to the surface of an insulating substrate (ceramic substrate) 102a and a back conductive film 102c is bonded to the back surface (metal patterns 102b and 102c on the front and back surfaces). is there.
- Reference numeral 104 denotes a semiconductor chip (semiconductor power chip) mounted on the conductive pattern 102 b of the insulating substrate with conductive pattern 102 via the solder 105.
- a resin case 106 accommodates a cooling base (metal base plate) 101 bonded to the back surface conductive film 102c of the insulating substrate with a conductive pattern (ceramic insulating substrate) 102 via the solder 103.
- Reference numeral 107 denotes a metal bar terminal which is an external lead-out terminal joined to the conductive pattern 102 b by solder 105.
- the semiconductor chips 104 or the conductive pattern 102b in a different region from the semiconductor chip 104 are joined by a bonding wire 108.
- Patent Document 1 describes a semiconductor device in which a semiconductor chip is arranged on an insulating substrate with a conductive pattern, a large number of metal pins are fixed to the semiconductor chip or the conductive pattern, and the large number of metal pins are fixed to a printed circuit board. ing. It is described that the wiring inductance can be reduced by arranging the metal foils attached to the front and back of the printed board so as to face each other in the printed board.
- Patent Documents 2 and 3 disclose that an external lead terminal of a P electrode and an external lead electrode terminal of an N electrode are arranged in parallel in a semiconductor device to reduce wiring inductance.
- the wiring inductance is the sum of the inductances of individual members such as an insulating substrate with a conductive pattern, bonding wires, and external lead-out terminals, and it is difficult to realize low inductance.
- Patent Documents 1, 2, and 3 a metal bar disposed on the front surface of a printed board with metal pins and a metal foil disposed on the back surface of the printed circuit board with metal pins opposed to each other on a semiconductor chip are used. There is no description of reducing the wiring inductance and further downsizing the semiconductor device by combining the configuration in which the formed external lead-out terminals (P terminal and N terminal, U terminal and P terminal, N terminal, etc.) are arranged adjacently in parallel. .
- An object of the present invention is to provide a semiconductor device having a printed circuit board with metal pins that can solve the above-described problems and reduce wiring inductance and achieve miniaturization.
- a semiconductor device has the following characteristics.
- An insulating substrate with a conductive pattern having at least a first conductive pattern, a second conductive pattern, and a third conductive pattern on the first insulating substrate, an external lead terminal of a positive electrode fixed to the first conductive pattern, and the second conductive pattern A negative external lead terminal fixed to the third conductive pattern, an intermediate potential external lead terminal fixed to the third conductive pattern, a first semiconductor element having one surface fixed to the first conductive pattern, and a third conductive pattern
- a conductive pin-equipped insulating substrate having a plurality of second conductive pins fixed to a conductive layer on the front surface of the second insulating substrate, wherein the positive lead-out terminal and the negative
- a part of the pin constituting the second conductive pin is fixed to the other surface of the second semiconductor element, and another pin constituting the second conductive pin is fixed to the conductive pattern. 2 is fixed to the conductive pattern, and the insulating substrate with conductive pins is disposed on the other surface side of the first semiconductor element and on the other surface side of the second semiconductor element.
- the size of the region where the semiconductor element is disposed is substantially the same as the size of the surface of the insulating substrate with conductive pins.
- the positive external lead-out terminal and the negative external lead-out terminal are arranged adjacent to and parallel to each other, and a part of the pin constituting the first conductive pin is on the other surface of the first semiconductor element.
- the other pin constituting the first conductive pin is fixed to the third conductive pattern, and a part of the pin constituting the second conductive pin is the other surface of the second semiconductor element. And other pins constituting the second conductive pins are fixed to the second conductive pattern, and the insulating substrate with conductive pins is connected to the other surface of the first semiconductor element and the second semiconductor. It is sandwiched between the other surfaces of the element.
- the semiconductor device according to the present invention is the above-described invention, wherein the insulating substrate with conductive pins is a metal foil fixed to the front surface and the back surface of the second insulating substrate made of ceramic, and the metal foil on the back surface. It is good that it is a printed circuit board with a metal pin which has the 1st metal pin fixed to the 2nd metal pin fixed to the metal foil of the front surface.
- the external lead terminal of the positive electrode and the external lead terminal of the negative electrode may be rectangular conductive plates.
- the first semiconductor element and the second semiconductor element are connected in series via the first conductive pin and the third conductive pattern in the above-described invention, and the upper arm or the lower arm
- the semiconductor module may be any one of 2in1, 4in1 and 6in1.
- the first semiconductor element and the second semiconductor element may each be composed of a switching transistor chip and a diode chip connected in reverse parallel to the switching transistor chip.
- the switching transistor chip is any of an IGBT chip, a MOSFET chip, a junction field effect transistor chip, or a bipolar transistor chip
- the diode chip is a pn diode chip.
- it may be a Schottky barrier diode chip.
- the semiconductor device in the above-described invention, it is preferable that three sides of the second conductive pattern are surrounded by the first conductive pattern.
- the second conductive pin fixed to the second conductive pattern penetrates the second insulating substrate.
- a semiconductor element is disposed on an insulating substrate with a conductive pattern
- the insulating substrate with a conductive pin is disposed above the insulating substrate with the conductive pattern on the side where the semiconductor element is disposed
- a plurality of insulating substrates with a conductive pattern are disposed on the insulating substrate with a conductive pattern.
- the insulating substrate with conductive pins can be made smaller, and the semiconductor device can be downsized. can do.
- a plurality of semiconductor elements are fixed to insulating plates with different conductive patterns, the semiconductor elements are opposed to each other with an insulating substrate with conductive pins interposed therebetween, and the conductive pins are fixed to the respective semiconductor elements and the conductive patterns.
- a semiconductor device having a small inductance and a small floor area can be manufactured.
- FIG. 7 is a cross-sectional view of a principal part taken along line XX of FIG. It is the top view which looked at the metal foil and metal pin of the front surface of the printed circuit board with a metal pin from the direction of arrow P of FIG. It is the top view which looked at the metal foil and metal pin of the back surface of the printed circuit board with a metal pin from the direction of arrow P of FIG. It is the top view of the back surface side which looked at the metal foil and metal pin of each of the front surface of a printed circuit board with a metal pin, and a back surface from the direction of arrow Q of FIG.
- FIG. 1 It is a circuit diagram of a semiconductor module incorporating a three-phase inverter circuit, and a diagram showing a current flow during steady operation. It is a figure which shows the path
- FIG. 3 is a main part configuration diagram showing a modification of the semiconductor module 100 of the first embodiment of the present invention, where (a) is a plan view of the main part, and (b) is a cross section of the main part taken along line XX of (a).
- FIG. It is principal part sectional drawing of the conventional semiconductor device.
- FIG. 1A and 1B are main part configuration diagrams of a semiconductor module device 100 according to a first embodiment of the present invention.
- FIG. 1A is a plan view of the main part
- FIG. 1B is an XX of FIG. It is principal part sectional drawing cut
- the printed circuit board 13 with metal pins is shown by a dotted line
- members below the printed circuit board 13 with metal pins are shown by a solid line.
- FIG. 2 is a plan view of the metal foil and the metal pin of the printed circuit board 13 with the metal pin as viewed from the direction of the arrow P in FIG. 1B.
- FIG. 2A is the metal foil and the metal pin on the front surface.
- FIG. 4B is a diagram showing a metal foil and a metal pin on the back surface. In the figure, the gate terminal is not shown.
- FIG. 3 is a plan view of the back surface side of the metal foil and the metal pins on the front surface and the back surface of the printed board 13 with metal pins as viewed from the direction of the arrow Q in FIG.
- the semiconductor module device 100 shown in FIGS. 1 to 3 includes an upper arm in which an IGBT (insulated gate bipolar transistor) chip 9 and an FWD (free wheeling diode) chip 10 connected in reverse parallel to the IGBT chip 9 are combined.
- a 2-in-1 semiconductor module composed of a lower arm in which an IGBT chip 11 and an FWD chip 12 connected in reverse parallel to the IGBT chip 11 are combined (hereinafter, a set of IGBT and FWD connected in reverse parallel is referred to as a “semiconductor element”.
- the IGBT chips 9 and 11 have a collector terminal C on one side and an emitter terminal E on the other side.
- the FWD chips 10 and 12 include a cathode terminal K on one surface and an anode terminal A on the other surface.
- the conductive patterns 4, 5, 6 are formed on the front surface of the ceramic substrate 2, and the back conductive film 3 is formed on the back surface.
- the conductive pattern 5 is formed in an island shape surrounded by the conductive pattern 4. In some cases, a metal foil is bonded to these conductive patterns 4, 5, 6 and the back surface conductive film 3 to increase the thickness.
- the printed circuit board 13 with metal pins is formed by bonding metal foils 15 and 16 to the front surface and the back surface of an insulating substrate 14 made of ceramic, respectively.
- the printed circuit board 13 with metal pins has the metal foil 15 on the front surface and the metal foil 16 on the back surface opposed to each other in the printed circuit board 13.
- the printed circuit board 13 with metal pins is disposed on the semiconductor element side of the insulating substrate 1 with a conductive pattern.
- Metal pins 17, 18, 19, and 20 are fixed in the same direction on the metal foils 15 and 16 of the printed circuit board 13 with metal pins.
- These metal pins and metal foils may be conductive pins or conductors having a large electric conduction.
- the metal pins 17 and 20 are fixed to the metal foil 15 on the front surface, and the metal pins 18 and 19 are fixed to the metal foil 16 on the back surface and are electrically connected to the metal foil 15 and the metal foil 16, respectively.
- the metal pin 17 is fixed to the metal foil 15 and penetrates the insulating substrate 14.
- the external lead-out terminals include a P terminal 21, an N end 22, and a U terminal 23.
- the P terminal 21 and the N terminal 22 are arranged close to each other in parallel.
- the collector side of the IGBT chip 9, the cathode side of the FWD 10, and the P terminal 21 are fixed and electrically connected to the conductive pattern 4 on the insulating substrate with conductive pattern 1.
- An N terminal 22 is fixed and electrically connected to the conductive pattern 5.
- the collector side of the IGBT chip 11, the cathode side of the FWD chip 12, and the U terminal 23 are fixed and electrically connected to the conductive pattern 6.
- the metal pin 17 is fixed to the conductive pattern 5, and the metal pin 18 is fixed to the emitter side of the IGBT chip 9 and the anode side of the FWD chip 10 and is electrically connected to each other.
- the metal pin 19 is fixed to the conductive pattern 6, and the metal pin 20 is fixed to and electrically connected to the emitter side of the IGBT chip 11 and the anode side of the FWD chip 12.
- the IGBT chips 9 and 11 and the FWD chips 10 and 12 are fixed by solders 7 and 8 which are bonding materials. Of course, a bonding material or a sintered material other than solder may be used in place of the solders 7 and 8.
- the shape of the printed circuit board 13 with metal pins is selected so that the metal pins 17 to 20 can be easily connected to the IGBT chips 9 and 11, the FWD chips 10 and 12, and the conductive patterns 5 and 6, for example, square or rectangular.
- the printed circuit board 13 with metal pins is, for example, substantially the same size as the region surrounding the IGBT chips 9 and 11 and the FWD chips 10 and 12, and preferably, the metal pins 17 and 19 of the conductive patterns 5 and 6 are further fixed.
- the area is almost the same size as the area including the part. This region corresponds to, for example, the region indicated by the dotted line (reference numeral 13) in FIG.
- the tips of the P terminal 21, N terminal 22 and U terminal 23, which are external lead-out terminals, are exposed, and the whole is sealed with an epoxy resin 24 so that the back surface conductive film 3 of the insulating substrate 1 with a conductive pattern is exposed.
- the semiconductor module 100 is completed.
- FIG. 4 is a diagram showing a circuit diagram of the 2-in-1 semiconductor module 100 and the direction of a current that flows during commutation.
- FIG. 5 is a diagram showing a path of a current flowing in the 2-in-1 semiconductor module 100 during commutation.
- FIG. 5A shows a path of a current flowing in the front-side metal foil 15 and the back-side metal foil 16.
- FIG. 2B is a cross-sectional view showing a current path.
- the time of commutation refers to, for example, a case where the U-phase upper arm element (in this case, the IGBT chip 9) shifts to an off state and the W-phase upper arm element shifts to an on state.
- a dotted line indicates another arm constituting the three-phase inverter circuit.
- the current a flows through the conductive pattern 4
- the current b flows through the path of the metal pin 18 and the metal foil 16 and the metal pin 19 on the back surface
- the current c flows through the conductive pattern 6.
- the current d passes through the path of the V-phase lower arm element (IGBT-V) -N terminal 22-FWD chip 12-U terminal 23-load M. e and f flow, and the currents d, e, and f increase.
- the current d flows through the conductive pattern 5
- the current e flows through the path of the metal pin 17 and the metal foil 15 and the metal pin 20 on the front surface
- the current f flows through the conductive pattern 6 and flows into the U terminal 23.
- the voltage (L ⁇ ( ⁇ di / dt)) generated in the conductive pattern generated by the product of the decrease rate ( ⁇ di / dt) of the current b and the inductance (L) of the metal foil 16 is the increase rate of the current e. It is canceled out by the resulting magnetic flux and becomes smaller.
- the wiring inductance refers to inductance caused by wiring including self-inductance, mutual inductance, and stray inductance.
- the wiring inductance can be reduced by forming the P terminal 21 and the N terminal 22 which are external output terminals with metal bars (plates) and arranging them in parallel with each other. Further, by shortening the metal pins 17 to 20, the distance between the printed board 13 with metal pins and the conductive pattern 4 can be shortened, and the wiring inductance can be reduced.
- the metal foil 15 on the front surface and the metal foil 16 on the back surface of the printed circuit board 13 with metal pins are opposed to each other in the printed circuit board 13. Thereby, the wiring inductance which influences at the time of commutation can be reduced.
- di / dt is increased in the same way even in a large current element, the use of the semiconductor module 100 can suppress the generation of a large surge voltage.
- the printed board 13 with metal pins can be made smaller.
- the semiconductor module 100 can be reduced in size.
- a method for calculating the wiring inductance of the 2-in-1 semiconductor module 100 by simulation will be described.
- the inductance of the wiring connecting the P terminal 21 and the N terminal 22 is calculated by simulation. This inductance does not necessarily match the operating inductance when two or three semiconductor modules 100 are connected to form a single-phase inverter circuit or a three-phase inverter circuit, but at least the inductance calculated by this simulation If is small, it has been confirmed that the inductance during operation is also small.
- the inductance calculated by the simulation is much lower in the semiconductor module 100 of the present invention.
- the inductance reduction is about 1/8 to 1/5 of the conventional semiconductor module 500, for example.
- FIGS. 6 and 7 are configuration diagrams of a semiconductor device according to a second embodiment of the present invention.
- FIG. 6 is a plan view of the main part, and FIG. .
- the printed circuit board 13a with metal pins is shown by a dotted line, and members below the printed circuit board 13a with metal pins are shown by a solid line.
- 8 and 9 are configuration diagrams of the printed circuit board 13a with metal pins.
- FIG. 8 is a plan view of the metal foil and the metal pins on the front surface as viewed from the direction of the arrow P in FIG. 7, and FIG. It is the top view which looked at metal foil and the metal pin from the direction of arrow P of FIG.
- FIG. 10 is a plan view of the back surface side of the metal foil and the metal pins on the front surface and the back surface of the printed circuit board 13a with metal pins as viewed from the direction of the arrow Q in FIG.
- FIG. 6, FIG. 7 and FIG. 1 The difference between FIG. 6, FIG. 7 and FIG. 1 is that the IGBT chip and FWD chip built in 2 in 1 of FIG. 1 are arranged in the U phase, V phase, and W phase. The number of metal pins 17 is tripled.
- the semiconductor device 200 includes a U phase, a V phase, and a W phase.
- the U phase an upper arm in which an IGBT chip 9a and an FWD chip 10a connected in reverse parallel to the IGBT chip 9a are combined (semiconductor element), and an FWD chip 12a connected in reverse parallel to the IGBT chip 11a is combined.
- the V-phase is constituted by an upper arm and a lower arm in which IGBT chips 9b and 11b and FWD chips 10b and 12b connected in reverse parallel to the IGBT chips 9b and 11b are combined.
- the W phase is composed of an upper arm and a lower arm, each of which is a set of IGBT chips 9c, 11c and FWD chips 10c, 12c connected in reverse parallel to the IGBT chips 9c, 11c.
- conductive patterns 4a, 5a, 6a, 6b, 6c are formed on the front surface of the ceramic substrate 2a, and a back conductive film 3a is formed on the back surface.
- the conductive pattern 5a is formed in an island shape surrounded by the conductive pattern 4a.
- a metal foil is bonded to the conductive patterns 4a, 5a, 6a, 6b, 6c and the back conductive film 3a to increase the thickness.
- the printed circuit board 13a with metal pins is formed by bonding metal foils 15a and 16a to the front surface and the back surface of an insulating substrate 14a made of ceramic, respectively.
- the printed circuit board 13a with metal pins has the front surface metal foil 15a and the rear surface metal foil 16a opposed to each other in the printed circuit board 13a.
- the printed circuit board 13a with metal pins is arranged on the semiconductor element side of the insulating substrate with conductive pattern 1a. Metal pins 17, 18, 19, and 20 are fixed to the metal foils 15a and 16a in the same direction.
- the metal pins 17 and 20 are fixed to the metal foil 15a on the front surface, and the metal pins 18 and 19 are fixed to the metal foil 16a on the back surface and are electrically connected to the metal foil 15a and the metal foil 16a, respectively.
- the metal pin 17 is fixed to the metal foil 15a and penetrates the insulating substrate 14a.
- the external lead-out terminals include a P terminal 21a, an N end 22a, a U terminal 23a, a V terminal 23b, and a W terminal 23c.
- the P terminal 21a and the N terminal 22a are arranged close to each other in parallel.
- the collector side of the IGBT chips 9a, 9b, 9c, the cathode side of the FWD chips 10a, 10b, 10c and the P terminal 21a are fixed and electrically connected to the conductive pattern 4a on the insulating substrate with conductive pattern 1a.
- An N terminal 22a is fixed and electrically connected to the conductive pattern 5a.
- the collector side of the IGBT chips 11a, 11b, and 11c, the cathode side of the FWD chips 12a, 12b, and 12c, and the U terminal 23a, the V terminal 23b, and the W terminal 23c are fixed and electrically connected to the conductive patterns 6a, 6b, and 6c, respectively.
- the IGBT chip and the FWD chip are fixed to each conductive pattern with solder 7a as a bonding material.
- the metal pin 17 is fixed to the conductive pattern 5a, and the metal pin 18 is fixed to the emitter side of the IGBT chips 9a, 9b, and 9c and the anode side of the FWD chips 10a, 10b, and 10c with solder 8a as a bonding material.
- the metal pin 19 is fixed to the conductive pattern 6a, and the metal pin 20 is fixed to the emitter side of the IGBT chips 11a, 11b, and 11c and the anode side of the FWD chips 12a, 12b, and 12c with solder 8a that is a bonding material. Connected.
- An epoxy resin 24a is used so that the tips of the P terminal 21a, the N terminal 22a, the U terminal 23a, the V terminal 23b, and the W terminal 23c, which are external lead-out terminals, are exposed and the back surface conductive film 3a of the insulating substrate with conductive pattern 1a is exposed. The whole is sealed, and a 6 in 1 semiconductor module 200 is completed.
- FIG. 11 is a circuit diagram of a semiconductor module incorporating a three-phase inverter circuit and a diagram showing a current flow during steady operation.
- FIG. 12 is a diagram illustrating a current path during steady operation and commutation using FIG. 7.
- the current input from the P terminal 21a flows out from the U terminal 23a to the load M, for example. Then, for example, the current returned from the load M to the V terminal 23b returns to the N terminal 22a. Specifically, the current a of the conductive pattern 4a enters the metal foil 16a through the IGBT chip 9a, and the current b of the metal foil 16a enters the conductive pattern 6a through the metal pin 19. The current c entering the conductive pattern 6a flows to the load M through the U terminal 23a.
- the current g returned from the load M enters the IGBT chip 11b through the conductive pattern 6b.
- the current h that has entered the metal foil 15a from the IGBT chip 11b passes through the metal pin 17 and enters the conductive pattern 5a.
- the current i entering the conductive pattern 5a flows out from the N terminal 22a to the external circuit.
- the current a flowing in the conductive pattern 4a and the current h of the metal foil 15a on the front surface are opposite (B portion). Further, the current b flowing through the metal foil 16a on the back surface and the current h flowing through the metal foil 15a on the front surface are in the opposite directions (C portion). Furthermore, the current a flowing through the P terminal 21a and the current i flowing through the N terminal 22a are also opposite (A part). Therefore, the wiring inductance is reduced during steady operation.
- FIG. 13 is a fragmentary cross-sectional view of the semiconductor device according to the third embodiment of the present invention.
- This semiconductor device is a 2 in 1 semiconductor module 300.
- two insulating substrates with conductive patterns (ceramic insulating substrates) 1d and 1e were used, and a circuit was configured in the vertical direction so as to minimize the area of the printed board 13d with metal pins.
- the collector side of the IGBT chip 9d and the cathode side of the FWD chip are fixed with solder 7d.
- the collector side of the IGBT chip 11d and the cathode side of the FWD chip are fixed with solder 7d.
- the printed circuit board 13d with metal pins is formed by bonding metal foils 15d and 16d to the front surface and the back surface of an insulating substrate 14d made of ceramic, respectively. Accordingly, the printed circuit board 13d with metal pins has the front surface metal foil 15d and the back surface metal foil 16d opposed to each other in the printed circuit board 13d. Metal pins 17d, 18d, 19d, and 20d are fixed and electrically connected to the printed board 13d with metal pins.
- the metal pin 18d and the emitter side of the IGBT chip 9d and the anode side of the FWD chip (not shown) are fixed with solder 8d, and the metal pin 20d and the emitter side of the IGBT chip 11d and the anode side of the FWD chip (not shown) are fixed with solder 8d. , Each is electrically connected.
- the metal pin 17d is fixed to the metal foil 15d and penetrates through the insulating substrate 14d.
- the metal pin 19d is fixed to the metal foil 16d and penetrates through the insulating substrate 14d.
- the P terminal 21d is fixed and electrically connected to the conductive pattern 4d of the insulating substrate with conductive pattern 1d.
- a metal pin 17d and an N terminal 22d are fixed to and electrically connected to the conductive pattern 5d.
- the P terminal 21d and the N terminal 22d are adjacently arranged in parallel and are formed of a metal bar (plate).
- the U terminal 23d and the metal pin 19d are fixed and electrically connected to the conductive pattern 6d of the insulating substrate with conductive pattern 1e.
- the conductive pattern 5d is formed in an island shape surrounded by the conductive pattern 4d.
- Insulating substrates 1d and 1e with conductive patterns are arranged on both sides of printed board 13d with metal pins, and semiconductor elements (IGBT chips 9d and 11d and FWD chips (IGBT in FIG. 13) are disposed on the insulating substrates 1d and 1e with conductive patterns. Chips 9d and 11d are located behind) and are electrically connected.
- the semiconductor module 300 is completed by sealing the whole with resin 24d.
- the height of the semiconductor module 300 is increased, but the floor area (footprint) of the semiconductor module 300 is significantly reduced, which contributes to size reduction in a system in which the semiconductor module 300 is incorporated. it can.
- FIG. 14 is a diagram illustrating current paths in the semiconductor device of FIG. 13 during commutation (solid line) and other than commutation (dotted line).
- the current a entered from the P terminal 21d enters the metal pin 18d through the conductive pattern 4d of the insulating substrate with conductive pattern 1d.
- the current b that has entered the metal foil 16d on the back side of the printed circuit board 13d with the metal pin from the metal pin 18d flows out of the metal pin 19d.
- the current c flowing out from the metal pin 19d flows through the conductive pattern 6d to the U terminal 23d.
- the current d enters the conductive pattern 5d from the N terminal 22d.
- a current e flowing from the conductive pattern 5d to the FWD chip (not shown in the figure) through the metal pin 17b, the metal foil 15d on the front surface, and the metal pin 20d flows to the conductive pattern 6d.
- the current f flowing through the conductive pattern 6d flows to the U terminal 23d.
- the voltage (L ⁇ ( ⁇ di / dt)) generated in the conductive pattern generated by the product of the decrease rate ( ⁇ di / dt) of the current b and the inductance (L) of the metal foil 16d is the increase rate of the current f. It is canceled out by the resulting magnetic flux and becomes smaller.
- the wiring inductance is reduced, and the conductive patterns 4d and 6d and the metal foils 15d and 16d at the time of commutation. Can be reduced in voltage.
- the jumping voltage (surge voltage) when the IGBT chip 9d shifts to the off state can be suppressed.
- the wiring inductance can be reduced by forming the P terminal 21d and the N terminal 22d, which are external output terminals, by metal bars (plates) and arranging them parallel to each other.
- the distance between the printed circuit board with metal pin 13d and the conductive patterns 4d and 6d can be reduced, and the inductance of the wiring can be reduced.
- the 2-in-1 semiconductor module 300 is described. However, this structure can also be applied to 4-in-1 and 6-in-1 semiconductor modules.
- the IGBT chip and the FWD chip are exemplified as the semiconductor elements.
- a MOSFET (field effect transistor) chip and a J-FET (junction field effect transistor) chip are used instead of the IGBT chip.
- a switching transistor chip such as a bipolar transistor chip may be used.
- Examples of the FWD chip include a pn diode chip and a Schottky barrier diode chip.
- the example of the 2-in-1 semiconductor module 100 and the second example of the 6-in-1 semiconductor module 200 have been described.
- four semiconductor elements a combination of an IGBT chip and an FWD chip
- the present invention can also be applied to a 4-in-1 semiconductor module.
- the example in which the conductive patterns 5, 5a, and 5d are formed in an island shape surrounded by the conductive patterns 4, 4a, and 4d has been described. It is not always necessary to be surrounded by the conductive patterns 4, 4a, 4d, and other modes may be used.
- the conductive pattern 4 is U-shaped and the conductive pattern 5 is surrounded by the conductive pattern 4. Good.
- a further smaller semiconductor device can be provided.
Abstract
Description
しかし、図16の半導体装置では、配線インダクタンスは導電パターン付絶縁基板、ボンディングワイヤおよび外部導出端子などの部材単体のインダクタンスの合算となり低インダクタンスを実現することは難しい。
<実施例1>
図1は、この発明の第1実施例の半導体モジュール装置100の要部構成図であり、同図(a)は要部平面図、同図(b)は同図(a)のX-X線で切断した要部断面図である。図1は、この発明の理解を容易にするために、金属ピン付プリント基板13を点線で示し、金属ピン付プリント基板13より下方の部材を実線で示した。
図1~3に示す、この半導体モジュール装置100は、IGBT(絶縁ゲート型バイポーラトランジスタ)チップ9とIGBTチップ9に逆並列接続するFWD(フリーホイーリングダイオード)チップ10とを組にした上アームと、IGBTチップ11とIGBTチップ11に逆並列接続するFWDチップ12とを組にした下アームとにより構成された2in1半導体モジュールである(以下、逆並列接続したIGBTとFWDの組を「半導体素子」ともいう。)。IGBTチップ9,11は、その一方の面にコレクタ端子Cを備え、他方の面にエミッタ端子Eを備えている。FWDチップ10,12は、その一方の面にカソード端子Kを備え、他方の面にアノード端子Aを備えている。導電パターン付絶縁基板1ではセラミック基板2のおもて面に導電パターン4,5,6が形成され、裏面に裏面導電膜3が形成されている。導電パターン5は、導電パターン4に囲まれて島状に形成されている。これらの導電パターン4,5,6や裏面導電膜3に金属箔を接合して、厚みを厚くした導電体とする場合もある。
金属ピン付プリント基板13の形状は、金属ピン17~20をIGBTチップ9,11、FWDチップ10,12および導電パターン5,6に接続しやすいように選択され、例えば正方形あるいは長方形である。金属ピン付プリント基板13は、例えば、IGBTチップ9,11とFWDチップ10,12を囲む領域とほぼ同じ大きさであり、好ましくは、さらに導電パターン5,6の金属ピン17、19が固着された部分を含む領域とほぼ同じ大きさである。この領域は、例えば図1(a)の点線(符号13)で示した領域に相当する。
図5は、転流時に2in1の半導体モジュール100内に流れる電流の経路を示す図であり、同図(a)はおもて面側の金属箔15と裏側の金属箔16に流れる電流の経路を示す平面図、同図(b)は電流の経路を示す断面図である。
また、点線は3相インバータ回路を構成する他のアームを示している。
また、金属ピン17~20を短くすることで、金属ピン付プリント基板13と導電パターン4の間の距離を縮めて、配線インダクタンスを小さくできる。
図6および図7は、この発明の第2実施例の半導体装置の構成図であり、図6は要部平面図、図7は図6のX-X線で切断した要部断面図である。図6は、この発明の理解を容易にするために、金属ピン付プリント基板13aを点線で示し、金属ピン付プリント基板13aより下方の部材を実線で示した。図8および図9は、金属ピン付プリント基板13aの構成図であり、図8はおもて面の金属箔と金属ピンを図7の矢印Pの方向から見た平面図、図9は裏面の金属箔と金属ピンを図7の矢印Pの方向から見た平面図である。
図10は、金属ピン付プリント基板13aのおもて面と裏面のそれぞれの金属箔と金属ピンを図7の矢印Qの方向から見た裏面側の平面図である。
図12は、図7を用いて、定常動作時と転流時の電流の経路を示す図である。
そのため、6in1の半導体モジュール200では、定常動作時において、配線インダクタンスは低減できる。
図13は、この発明の第3実施例の半導体装置の要部断面図である。この半導体装置は2in1の半導体モジュール300である。この半導体モジュール300は、2個の導電パターン付絶縁基板(セラミック絶縁基板)1d,1eを使用し、金属ピン付プリント基板13dの面積を最小限とするよう縦方向に回路を構成した。
導電パターン付絶縁基板1e上にIGBTチップ11dのコレクタ側と図示しないFWDチップのカソード側を半田7dで固着する。
図14は、図13の半導体装置で、転流時(実線)と転流時以外(点線)の電流の経路を示す図である。P端子21dから入った電流aは導電パターン付絶縁基板1dの導電パターン4dを通って金属ピン18dに入る。金属ピン18dから金属ピン付プリント基板13dの裏側の金属箔16dに入った電流bは金属ピン19dから流れ出す。金属ピン19dから流れ出した電流cは導電パターン6dを通ってU端子23dへ流れてゆく。
さらに、外部出力端子であるP端子21d、N端子22dを金属バー(板)で形成し互いに平行に配置することにより、配線インダクタンスを低減することができる。
尚、実施例3では2in1の半導体モジュール300について記載したが、この構造は4in1および6in1の半導体モジュールにも適用できる。
また、実施例1では2in1の半導体モジュール100、実施例2では6in1の半導体モジュール200の例を説明したが、半導体素子(IGBTチップとFWDチップの組み合わせたもの)が4個が同一パッケージに収納された4in1の半導体モジュールにも本発明は適用できる。
2,2a,2d,2e セラミック基板(第1絶縁基板)
3,3a 裏面導電膜
4,4a,4d 導電パターン(第1導電パターン)
5,5a,5d 導電パターン(第2導電パターン)
6,6a,6b,6c,6d 導電パターン(第3導電パターン)
7,7a,7d,8,8a,8d 半田
9,9a,9d,11,11a,11d IGBTチップ
10,10a,12,12a FWDチップ
13,13a,13d 金属ピン付プリント基板(導電ピン付絶縁基板)
14,14a,14d 絶縁基板(第2絶縁基板)
15,15a,15d おもて面の金属箔(導電層)
16,16a 裏面の金属箔(導電層)
17,17d 金属ピン(第2導電ピン)
18,18d 金属ピン(第1導電ピン)
19,19d 金属ピン(第1導電ピン)
20,20d 金属ピン(第2導電ピン)
21,21a,21d P端子(正極の外部導出端子)
22,22a,22d N端子(負極の外部導出端子)
23,23a,23d U端子(中間電位の外部導出端子)
23b V端子
23c W端子
24,24a エポキシ樹脂
24d 樹脂
100,200、300 半導体モジュール
a~i,r 電流
Claims (9)
- 少なくとも第1導電パターン、第2導電パターンおよび第3導電パターンを第1絶縁基板上に有する導電パターン付絶縁基板と、前記第1導電パターンに固着した正極の外部導出端子と、前記第2導電パターンに固着した負極の外部導出端子と、前記第3導電パターンに固着した中間電位の外部導出端子と、前記第1導電パターンに一方の面が固着した第1半導体素子と、前記第3導電パターンに一方の面が固着した第2半導体素子と、第2絶縁基板の裏面とおもて面にそれぞれ導電層を有し、前記第2絶縁基板の裏面の導電層に固着した複数の第1導電ピンおよび前記第2絶縁基板のおもて面の導電層に固着した複数の第2導電ピンを有する導電ピン付絶縁基板と、を具備し、
前記正極の外部導出端子と負極の外部導出端子が互いに隣接して平行に配置されており、前記第1導電ピンを構成するピンの一部が前記第1半導体素子の他方の面に固着しているとともに該第1導電ピンを構成する他のピンが前記第3導電パターンに固着しており、前記第2導電ピンを構成するピンの一部が前記第2半導体素子の他方の面に固着しているとともに該第2導電ピンを構成する他のピンが前記第2導電パターンに固着しており、前記導電ピン付絶縁基板が前記第1半導体素子の他方の面側および第2半導体素子の他方の面側に配置されており、該第1半導体素子および第2半導体素子が配置された領域の大きさと前記導電ピン付絶縁基板面の大きさがほぼ同じであることを特徴とする半導体装置。 - 少なくとも第1導電パターンおよび第2導電パターンを第1絶縁基板上に有する第1導電パターン付絶縁基板と、少なくとも第3導電パターンを第3絶縁基板上に有する第2導電パターン付絶縁基板と、前記第1導電パターンに固着した正極の外部導出端子と、前記第2導電パターンに固着した負極の外部導出端子と、前記第3導電パターンに固着した中間電位の外部導出端子と、前記第1導電パターンに一方の面が固着した第1半導体素子と、前記第3導電パターンに一方の面が固着した第2半導体素子と、第2絶縁基板の裏面とおもて面にそれぞれ導電層を有し、前記第2絶縁基板の裏面の導電層に固着した複数の第1導電ピンおよび前記第2絶縁基板のおもて面の導電層に固着した複数の第2導電ピンを有する導電ピン付絶縁基板と、を具備し、
前記正極の外部導出端子と負極の外部導出端子が互いに隣接して平行に配置されており、前記第1導電ピンを構成するピンの一部が前記第1半導体素子の他方の面に固着しているとともに該第1導電ピンを構成する他のピンが前記第3導電パターンに固着しており、前記第2導電ピンを構成するピンの一部が前記第2半導体素子の他方の面に固着しているとともに該第2導電ピンを構成する他のピンが前記第2導電パターンに固着しており、前記導電ピン付絶縁基板が前記第1半導体素子の他方の面と前記第2半導体素子の他方の面の間に挟まれて配置されていることを特徴とする半導体装置。 - 前記導電ピン付絶縁基板が、セラミックからなる前記第2絶縁基板のおもて面と裏面にそれぞれ固着した金属箔と、裏面の金属箔に固着した第1金属ピンと、おもて面の金属箔に固着した第2金属ピンと、を有する金属ピン付プリント基板であることを特徴とする請求項1または2に記載の半導体装置。
- 前記正極の外部導出端子および前記負極の外部導出端子が、長方形の導電板であることを特徴とする請求項1または2に記載の半導体装置。
- 前記第1半導体素子と前記第2半導体素子が前記第1導電ピンおよび前記第3導電パターンを介して直列接続し、上アームまたは下アームを構成している2in1,4in1もしくは6in1のいずれかの半導体モジュールであることを特徴とする請求項1または2に記載の半導体装置。
- 前記第1半導体素子および第2半導体素子のそれぞれが、スイッチングトランジスタチップと該スイッチングトランジスタチップに逆並列接続するダイオードチップからなることを特徴とする請求項1または2に記載の半導体装置。
- 前記スイッチングトランジスタチップが、IGBTチップ、MOSFETチップ、接合型電界効果トランジスタチップもしくはバイポーラトランジスタチップのいずれかであり、前記ダイオードチップがpnダイオードチップもしくはショットキーバリアダイオードチップであることを特徴とする請求項6に記載の半導体装置。
- 前記第2導電パターンの3方が、前記第1導電パターンに囲まれていることを特徴とする請求項1または2に記載の半導体装置。
- 前記第2導電パターンに固着している前記第2導電ピンが、前記第2絶縁基板を貫通していることを特徴とする請求項1または2に記載の半導体装置。
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Also Published As
Publication number | Publication date |
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CN104040715B (zh) | 2017-02-22 |
JP5971263B2 (ja) | 2016-08-17 |
US20150243640A1 (en) | 2015-08-27 |
EP2814059A4 (en) | 2015-10-14 |
JPWO2013118415A1 (ja) | 2015-05-11 |
US9059009B2 (en) | 2015-06-16 |
US20140346676A1 (en) | 2014-11-27 |
CN104040715A (zh) | 2014-09-10 |
KR20140123935A (ko) | 2014-10-23 |
US9305910B2 (en) | 2016-04-05 |
KR101926854B1 (ko) | 2018-12-07 |
EP2814059B1 (en) | 2020-08-05 |
EP2814059A1 (en) | 2014-12-17 |
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