WO2014090065A1 - Pre-decoding analysis-based data information cache management method and system - Google Patents
Pre-decoding analysis-based data information cache management method and system Download PDFInfo
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- the invention belongs to the field of embedded reconfigurable design, and particularly relates to a data information cache management method and system based on pre-decoding analysis, and more particularly to a data information cache management method based on pre-decoding analysis in a media processing reconfigurable system. And system.
- GPP General Purpose Processors
- ASIC Application Specific Integrated Circuit
- Optimizing the reconfigurable storage subsystem, reducing access latency is mainly considered from two aspects: 1. Access to the characteristics of the external memory itself; 2. The inherent data flow characteristics of the media algorithm.
- SDRAM synchronous synchronous random access memory
- synchronous dynamic random access memory For synchronous dynamic random access memory, it has the following characteristics: 1. It is composed of Bank, Page and Column. (column) These three basic units are constructed; 2. It supports continuous reading and writing in Burst mode.
- these two features can be fully utilized to improve the performance of chips with synchronous dynamic random access memory. Due to feature 1, the number of external memories should be minimized and the paging delay caused by data access should be reduced. Due to feature 2, the burst length of the access memory is maximized, and the fixed delay caused by multiple accesses is reduced. Therefore, when accessing the synchronous dynamic random access memory structure as an external memory, the above two characteristics should be considered as much as possible to improve data access efficiency.
- the same reference frame data is used multiple times, for example, predicting an 8 ⁇ 8 luminance block in H.264, then it is in the worst case.
- an object of the present invention is to provide a data information cache management method and system based on pre-decoding analysis, which reduces data transmission time and reduces data bandwidth occupation by utilizing duplicate data as much as possible. And the line-over delay in the external memory to improve the data access efficiency of the large-scale coarse-grained reconfigurable system, resulting in improved performance.
- the first technical solution adopted by the present invention is a data information cache management system based on pre-decoding analysis, including a streaming media processor module and a data input prefetch FIFO (First Input First Output, First in first out queue) module, data information cache unit and data information cache controller module;
- FIFO First Input First Output, First in first out queue
- the streaming media processor module is configured to parse a macroblock in a code stream obtained from an external memory, generate a data information entry corresponding to the macroblock, and output the data information entry to a data information prefetch FIFO module;
- the data information prefetch FIFO module is configured to sequentially store data information items generated by the streaming media processor module;
- the data information buffer unit is configured to cache a data block taken from an external memory
- the data information cache controller module is configured to: according to the data information entry in the data information FIFO module, determine that the required data information is all present in the data information cache unit, or partially exist or not all present in the data information In the buffer unit, and according to the judgment result, the corresponding data block in the data information buffer unit forms a data block required by the reconfigurable computing unit, and finally sent to the corresponding reconfigurable array.
- the data information prefetch FIFO module comprises A FIFO units, wherein A is an integer not less than 1, each of the FIFO units stores a data information item, and the data information item is referenced by a desired macro block.
- A is an integer not less than 1
- each of the FIFO units stores a data information item, and the data information item is referenced by a desired macro block.
- the frame number, horizontal and vertical position components are composed of the actual required macroblock size.
- the data information buffering unit includes two forward and backward buffer units applying bidirectional prediction, respectively storing forward prediction and backward prediction reference frame data, and each of the buffer units has B data blocks.
- the data information cache controller module includes a data information comparison unit, a data selector and data.
- the data information comparison unit is configured to compare the data information item in the data information prefetch FIFO module with the data block in the data information buffer unit, if the data block corresponding to the data information item is in the data information buffer unit If there exists, the data information comparison unit reads the data block; if only part of the data in the data block exists in the data information buffer unit or does not have any data in the data block, the corresponding hit information is sent to a data selector; the data selector selects data to be fetched from the external memory to the shifting, splicing unit, or directly to the data information buffer unit according to the partial hit or the complete miss information; the data shift, the splicing unit, the data In the case of partial hits, the data of the partial hits and the remaining data taken from the external memory are spliced into the data blocks required for the reconfigurable array.
- a second technical solution adopted by the present invention is a management method using a data information cache management system based on pre-decoding analysis as described above, including the following steps:
- the streaming media processor module parses a macroblock in a code stream obtained from an external memory, generates a data information entry corresponding to the macroblock, and outputs the data information entry to the data information pre- Take the FIFO module;
- the data information cache controller module extracts the data information item from the data information prefetch FIFO, and compares the data information item with the data block in the data information buffer unit, If the data block corresponding to the data information entry exists in the data information cache unit, the data information cache controller module reads the data block; if only part of the data in the data block exists in the data information cache unit, then Reusing data, the data information cache controller module initiates access to the external memory to obtain the remaining data, and combines the reused data and the remaining data into corresponding data blocks by shifting; if there is no data in the data information cache unit For any data in the data block, the data information cache controller module sends corresponding data information to the external memory controller, and obtains the data block; when the data information is replaced, the data information cache controller module hits according to the data. Prefer the data information buffer unit and the data letter preferentially The data block corresponding to the data entry does not match the data replacement;
- the data information buffer controller sequentially sends the data information in the read data block to the corresponding reconfigurable array
- the present invention utilizes pre-parsed macroblock data information to divide the data cache into complete misses, partial hits, and complete misses, respectively, to maximize data reuse, reducing data bandwidth occupation, and reducing
- the number of accesses to external memory improves the performance of large-scale coarse-grained reconfigurable systems.
- FIG. 1 is a schematic diagram of data information based on pre-decoding analysis in a media processing reconfigurable system according to an embodiment of the present invention. Schematic diagram of the structure;
- FIG. 2 is a schematic structural diagram of a data cache controller in a data information cache based on pre-decoding analysis in the media processing reconfigurable system shown in FIG. 1;
- FIG. 3 is a schematic diagram showing an entry of data information in a data information prefetching FIFO module in a data information buffer based on pre-decoding analysis in the media processing reconfigurable system shown in FIG. 1;
- FIG. 4 is a schematic diagram showing the data blocks in the data information buffer unit in the data information buffer based on the pre-decoding analysis in the media processing reconfigurable system shown in FIG. 1;
- FIG. 5 is a flowchart of a method for managing data information cache based on pre-decoding analysis in a media processing reconfigurable system according to an embodiment of the present invention
- FIG. 6 is a flowchart of updating a data block in a data buffer unit in a management method of data information cache based on pre-decoding analysis in a media processing reconfigurable system according to an embodiment of the present invention
- FIG. 7 is a connection diagram of an application of a data information cache structure based on pre-decoding analysis in a media processing reconfigurable system according to an embodiment of the present invention.
- a data information cache structure based on pre-decoding analysis in a media processing reconfigurable system includes a streaming media processor module: configured to parse a macroblock in a code stream obtained from an external memory, and generate and process the macroblock Corresponding macroblock layer data information, and outputting the macroblock layer data information to the data information prefetching FIFO module; the data information prefetching FIFO module: for sequentially storing the data information items generated by the streaming media processor module; Cache unit (referred to as "data cache unit”): used to cache data information blocks (referred to as "data blocks") taken from external memory; data information cache controller module: used to prefetch FIFO modules based on data information The data information item determines whether the required data information exists in the data information buffer unit, or exists partially in the data information buffer unit, or does not exist in the data information buffer unit at all. And by comparing the results, the corresponding data blocks in the data information buffer unit are shifted and combined to form a data information block required by the reconfigurable computing
- a data information cache controller (referred to as a "data cache controller") module includes a comparison, shift stitching, and data selection unit.
- the data cache controller obtains the corresponding hit information by comparing the data information pre-fetching the entry in the FIFO module with the data information in the data information buffer unit, and then transmitting the corresponding control information to the data selection unit, shifting, splicing unit and external Memory. If the data block corresponding to the entry exists in the data cache unit, the data cache controller reads the data block and sends it to the reconfigurable computing array; if there is only a partial hit, the reuse data is retained, and the access is initiated to the external memory.
- the data cache controller sends corresponding data information to the external memory, obtains the data block and sends it to the reconfigurable computing array and stores it in Data information cache unit.
- the data information prefetch FIFO module includes A FIFO units, each FIFO unit consists of a reference frame number P0C including a desired macroblock, horizontal and vertical position components (x, y), and actual required macros.
- the data size entry (referred to as "entry") formed by the three block sizes (MXN, M for the macroblock width and N for the height of the macroblock) is represented by entry.
- the data information buffering unit includes two forward and backward buffer units of bidirectional prediction, and each of the buffer units has B data blocks, and a total of 2 ⁇ B data blocks.
- Each cache unit is composed of specific data blocks. Parameters A and B are experimentally derived to obtain specific values, which results in the best yield.
- a data information cache management method generates a data information entry: the streaming media processor module parses a macroblock in a code stream obtained from an external memory, and generates macroblock layer data information corresponding to the macroblock. And outputting the macroblock layer data information to the data information prefetch FIFO module; querying, reading and replacing the data information: as shown in FIG.
- the data cache controller takes an entry from the data information prefetch FIFO, Comparing the content in the entry with the data block in the data cache unit, if the data block corresponding to the entry exists in the data cache unit, the data cache controller reads the data block; if only partial hits, the retained data is retained Initiating an access to the external memory to obtain the remaining data block, and combining the two into a corresponding data block by shifting; if it is completely missed, the data cache controller sends corresponding data information to the external memory controller, and obtains the data block.
- the data cache controller selects the data information in the data buffer unit that is not used for a period of time according to the data information prefetching the entry in the FIFO module, and replaces it.
- the data buffer controller sequentially sends the read complete data block to the corresponding reconfigurable array. Repeat the above steps until all the data blocks corresponding to the data information items have been sent.
- the three-stage operation mode is a pipeline mode, which fully utilizes the resources of the data information cache and improves the operation efficiency of the large-scale coarse-grained reconfigurable system.
- the HD digital video decoding of the H.264 protocol adopts the data information buffer structure based on the pre-decoding analysis in the media processing reconfigurable system proposed by the present invention.
- Management method capable of realizing HD video decoding requirements of H.264 1080p@30fps HiP@Level4.
- the structure of the system includes: ARM7TDMI processor used as the master, data information cache structure, reconfigurable array, custom external memory access interface, external memory.
- the ARM7TDMI processor with small, fast, low power consumption, and good compiler support is selected as the main control CPU for controlling the scheduling of system operation; the data information buffer is connected to the external memory through a 64-bit custom external memory interface bus.
- the external memory uses the most commonly used embedded external memory DDR SDRAM, which has good cost performance and energy consumption ratio; there are two reconfigurable computing units, each with 8 reconfigurable arrays, each of which has a reconfigurable array. 8 X 8 computing units.
- the corresponding stream Each time the processor generates a corresponding data information entry, the data information entry includes three parts, the width of which is 31 bits, the reference frame number is 8 bits, the horizontal and vertical components are 6 bits and 7 bits, respectively, and the width and height of the macro block are 5 bits.
- the Data Information Prefetch FIFO module contains 256 FIFO units with a total size of IK Bytes.
- the data information cache module contains 32 cache blocks, each of which has a data size of 16 x 16 bits.
- the comparison structure is not added to the data information cache structure, that is, the data is directly obtained from the external memory.
- the experimental results show that with the data information cache structure and the corresponding data information cache management method proposed by the present invention, the number of accesses to the external memory by the system is reduced by about 30%, and the bandwidth is saved by about 45%, so that the overall performance is improved by about 40%.
Abstract
Disclosed is a pre-decoding analysis-based data information cache management system, comprising a streaming media processor module, a data information prefetch FIFO module, a data information cache unit, and a data information cache controller module. Also disclosed is a management method for the pre-decoding analysis-based data information cache management system. By utilizing as much as possible repeated data, the present invention reduces data transmission time and reduces data bandwidth usage and wrapping latency in an external memory, thus increasing the efficiency of data access of a large-scale coarse grain reconfigurable system, and increasing performance.
Description
基于预先解码分析的数据信息缓存管理方法及系统 技术领域 Data information cache management method and system based on pre-decoding analysis
本发明属于嵌入式可重构设计领域， 具体涉及一种基于预先解码分析的数据信息缓 存管理方法及系统， 更具体涉及一种媒体处理可重构系统中基于预先解码分析的数据信 息缓存管理方法及系统。 The invention belongs to the field of embedded reconfigurable design, and particularly relates to a data information cache management method and system based on pre-decoding analysis, and more particularly to a data information cache management method based on pre-decoding analysis in a media processing reconfigurable system. And system.
背景技术 Background technique
将通用处理器（GPP， General Purpose Processors )的灵活性和专用集成电路（ASIC, Appl ication Specific Integrated Circuit ) 的高效性结合的一种计算体系结构， 可重 构计算架构近些年来在嵌入式系统设计方面获得了越来越广泛的关注， 其主要的应用领 域包括多媒体处理、 移动通信、 数字信号处理、 数据加解密等。 随着媒体应用的性能要 求和计算复杂度越来越高， 粗粒度可重构架构的计算资源也成倍增加， 一些架构使用了 多个可重构阵列来完成这些应用。 然而， 在计算资源增加的同时， 计算资源对于数据流 的要求也进一步增大。 随着处理器速度与存储器访问速度的差距不断增大， 面向应用的 系统级芯片中存储子系统的访问延迟已经成为可重构系统性能的瓶颈， 很大程度上限制 了整体性能的提升。 如何优化可重构系统存储子系统， 减少访问延迟成为可重构系统研 究的关键。 A computing architecture that combines the flexibility of GPP (General Purpose Processors) with the efficiency of an ASIC (Application Specific Integrated Circuit), reconfigurable computing architecture in embedded systems in recent years Design has gained more and more attention, and its main application areas include multimedia processing, mobile communication, digital signal processing, data encryption and decryption. As the performance requirements and computational complexity of media applications increase, the computational resources of coarse-grained reconfigurable architectures multiply, and some architectures use multiple reconfigurable arrays to accomplish these applications. However, as computing resources increase, the requirements for computing resources for data streams are further increased. As the gap between processor speed and memory access speed increases, the access latency of storage subsystems in application-oriented system-on-chip has become a bottleneck in the performance of reconfigurable systems, largely limiting overall performance. How to optimize reconfigurable system storage subsystems and reduce access latency becomes the key to reconfigurable system research.
优化可重构存储子系统， 减少访问延迟主要从两个方面来考虑： 1、 访问外部存储器 本身的特点； 2、 媒体算法固有的数据流特点。 Optimizing the reconfigurable storage subsystem, reducing access latency is mainly considered from two aspects: 1. Access to the characteristics of the external memory itself; 2. The inherent data flow characteristics of the media algorithm.
基于成本考虑， 目前作为外部存储器用的比较多的是同步动态随机存储器 （SDRAM) 结构， 对于同步动态随机存储器， 其主要有如下特点： 1、 它由 Bank (组）、 Page (页） 和 Column (列） 这三个基本单元构成； 2、 它支持以 Burst (猝发） 方式进行连续读写。 在外部存储接口设计中， 可以充分利用这两个特性来提高以同步动态随机存储器为外存 的芯片的性能。 由于特性 1， 应当尽量减少对外部存储器的次数， 减少数据访问时带来的 换页延迟。由于特性 2，尽量延长访问存储器的猝发长度，减少多次访问造成的固定延时。 因此在访问以同步动态随机存储器结构为外部存储器的时候， 应该尽量考虑以上两个特 性， 以提高数据访问效率。 Based on cost considerations, the current use of external memory is more synchronous synchronous random access memory (SDRAM) structure. For synchronous dynamic random access memory, it has the following characteristics: 1. It is composed of Bank, Page and Column. (column) These three basic units are constructed; 2. It supports continuous reading and writing in Burst mode. In the external memory interface design, these two features can be fully utilized to improve the performance of chips with synchronous dynamic random access memory. Due to feature 1, the number of external memories should be minimized and the paging delay caused by data access should be reduced. Due to feature 2, the burst length of the access memory is maximized, and the fixed delay caused by multiple accesses is reduced. Therefore, when accessing the synchronous dynamic random access memory structure as an external memory, the above two characteristics should be considered as much as possible to improve data access efficiency.
对于媒体算法， 主要有两个特点： 1、 按照宏块处理数据； 2、 参考图像会用到多次。 媒体数据图像在外部存储器中按帧存放， 每一帧图像按照光栅扫描方式存放在外部的同 步动态随机存储器中。 由于媒体算法按宏块处理， 而宏块中上下两行数据在地址空间中 不连续， 因此读取宏块时可能会引起多次换行。 例如， 假设每行同步动态随机存储器存 储 1024Byte数据，媒体像素数据大小为 IByte,则对于分辨率为 1080p即包含 1920*1080 像素的帧数据， 由于帧内每行数据都分布在不同的行中， 因此当读取帧内宏块时需要多
次换行， 由此造成严重的数据访问延迟。 由于媒体数据具有时间和空间局部性， 特别是 重建相邻宏块时， 会多次用到同一参考帧数据， 比如在 H. 264中预测一个 8 X 8的亮度 块， 那么它在最坏情况下需要参考数据为（8 + 5) X (8 + 5) =169 bytes。 如果将它分 割为 4个 4 X 4块进行处理， 那么它需要的参考数据为（4 + 5) X (4 + 5) X 4 = 324 Bytes, 它的重复数据达到 155 Bytes。 同理， 如果预测 16 X 16的亮度块， 相应情况下 其相应所需数据和重复数据分别为 441Bytes和 855Bytes，此时重复数据将达到有效数据 的 2倍。 For media algorithms, there are two main features: 1. Processing data according to macroblocks; 2. Reference images will be used multiple times. The media data images are stored in frames in an external memory, and each frame image is stored in an external synchronous dynamic random access memory in a raster scan manner. Since the media algorithm is processed in macroblocks, and the upper and lower two rows of data in the macroblock are not continuous in the address space, multiple line breaks may occur when the macroblock is read. For example, suppose that each line of synchronous dynamic random access memory stores 1024 Bytes of data, and the media pixel data size is IByte. For frame data with a resolution of 1080p, that is, 1920*1080 pixels, since each line of data in the frame is distributed in different lines, So you need more when reading intra macroblocks Second line breaks, resulting in severe data access delays. Since the media data has temporal and spatial locality, especially when reconstructing adjacent macroblocks, the same reference frame data is used multiple times, for example, predicting an 8×8 luminance block in H.264, then it is in the worst case. The reference data is (8 + 5) X (8 + 5) = 169 bytes. If it is divided into four 4 X 4 blocks for processing, then the reference data it needs is (4 + 5) X (4 + 5) X 4 = 324 Bytes, and its duplicate data reaches 155 Bytes. Similarly, if a 16 X 16 luma block is predicted, the corresponding required data and duplicate data are 441 Bytes and 855 Bytes, respectively, and the repeated data will reach twice the effective data.
发明内容 Summary of the invention
发明目的： 针对上述现有技术存在的问题和不足， 本发明的目的是提供一种基于预 先解码分析的数据信息缓存管理方法及系统， 通过尽量利用重复数据， 减少数据传输时 间， 减少数据带宽占用及在外部存储器中的换行延迟， 以提高大规模粗粒度可重构系统 的数据访问效率， 使得性能提升。 SUMMARY OF THE INVENTION In view of the above problems and deficiencies of the prior art, an object of the present invention is to provide a data information cache management method and system based on pre-decoding analysis, which reduces data transmission time and reduces data bandwidth occupation by utilizing duplicate data as much as possible. And the line-over delay in the external memory to improve the data access efficiency of the large-scale coarse-grained reconfigurable system, resulting in improved performance.
技术方案： 为实现上述发明目的， 本发明采用的第一种技术方案为一种基于预先解 码分析的数据信息缓存管理系统， 包括流媒体处理器模块、 数据信息预取 FIFO (First Input First Output , 先入先出队列） 模块、 数据信息缓存单元和数据信息缓存控制器 模块； Technical Solution: In order to achieve the above object, the first technical solution adopted by the present invention is a data information cache management system based on pre-decoding analysis, including a streaming media processor module and a data input prefetch FIFO (First Input First Output, First in first out queue) module, data information cache unit and data information cache controller module;
所述流媒体处理器模块： 用于解析从外部存储器取得的码流中的宏块， 生成处理该 宏块对应的数据信息条目， 并将该数据信息条目输出到数据信息预取 FIFO模块； The streaming media processor module is configured to parse a macroblock in a code stream obtained from an external memory, generate a data information entry corresponding to the macroblock, and output the data information entry to a data information prefetch FIFO module;
所述数据信息预取 FIFO模块：用于依次存储所述流媒体处理器模块生成的数据信息 条目； The data information prefetch FIFO module is configured to sequentially store data information items generated by the streaming media processor module;
所述数据信息缓存单元： 用于缓存从外部存储器中取到的数据块； The data information buffer unit is configured to cache a data block taken from an external memory;
所述数据信息缓存控制器模块： 用于根据数据信息 FIFO模块中的数据信息条目， 判 断所需的数据信息是全部存在于数据信息缓存单元中， 或者是部分存在或者是全部不存 在于数据信息缓存单元中， 并根据判断结果将数据信息缓存单元中相应的数据块形成可 重构计算单元所需的数据块， 最后发送至相应的可重构阵列。 The data information cache controller module is configured to: according to the data information entry in the data information FIFO module, determine that the required data information is all present in the data information cache unit, or partially exist or not all present in the data information In the buffer unit, and according to the judgment result, the corresponding data block in the data information buffer unit forms a data block required by the reconfigurable computing unit, and finally sent to the corresponding reconfigurable array.
优选的， 所述数据信息预取 FIFO模块包括 A个 FIFO单元， 其中 A为不小于 1的整 数， 每个所述 FIFO单元存储一个数据信息条目， 所述数据信息条目由所需宏块的参考帧 编号、 水平和垂直位置分量与实际所需宏块大小组成。 Preferably, the data information prefetch FIFO module comprises A FIFO units, wherein A is an integer not less than 1, each of the FIFO units stores a data information item, and the data information item is referenced by a desired macro block. The frame number, horizontal and vertical position components are composed of the actual required macroblock size.
优选的， 所述数据信息缓存单元包含应用双向预测的前向和后向两个缓存单元， 分 别存储前向预测和后向预测参考帧数据， 每个所述缓存单元中有 B个数据块， 一共有 2 X B个数据块 Preferably, the data information buffering unit includes two forward and backward buffer units applying bidirectional prediction, respectively storing forward prediction and backward prediction reference frame data, and each of the buffer units has B data blocks. A total of 2 XB data blocks
优选的， 所述数据信息缓存控制器模块包括数据信息比较单元， 数据选择器和数据
移位、拼接单元； 所述数据信息比较单元用于比较数据信息预取 FIFO模块中的数据信息 条目和数据信息缓存单元中的数据块， 如果此数据信息条目对应的数据块在数据信息缓 存单元中存在， 则数据信息比较单元读取该数据块； 如果在数据信息缓存单元中只存在 所述数据块中的部分数据或没有所述数据块中的任何数据， 则将相应的命中信息发送给 数据选择器； 数据选择器根据部分命中或者完全不命中信息选择将从所述外部存储器取 得的数据发送给移位、 拼接单元或者直接发送给数据信息缓存单元； 数据移位、 拼接单 元， 在数据部分命中时， 将部分命中的数据和从外部存储器取得的剩余数据拼接成可重 构阵列所需数据块。 Preferably, the data information cache controller module includes a data information comparison unit, a data selector and data. The data information comparison unit is configured to compare the data information item in the data information prefetch FIFO module with the data block in the data information buffer unit, if the data block corresponding to the data information item is in the data information buffer unit If there exists, the data information comparison unit reads the data block; if only part of the data in the data block exists in the data information buffer unit or does not have any data in the data block, the corresponding hit information is sent to a data selector; the data selector selects data to be fetched from the external memory to the shifting, splicing unit, or directly to the data information buffer unit according to the partial hit or the complete miss information; the data shift, the splicing unit, the data In the case of partial hits, the data of the partial hits and the remaining data taken from the external memory are spliced into the data blocks required for the reconfigurable array.
本发明采用的第二种技术方案为一种利用如上所述基于预先解码分析的数据信息缓 存管理系统的管理方法， 包括如下步骤： A second technical solution adopted by the present invention is a management method using a data information cache management system based on pre-decoding analysis as described above, including the following steps:
( 1 )生成数据信息条目： 所述流媒体处理器模块解析从外部存储器取得的码流中的 宏块， 生成处理该宏块对应的数据信息条目， 并将该数据信息条目输出到数据信息预取 FIFO模块； (1) Generating a data information entry: the streaming media processor module parses a macroblock in a code stream obtained from an external memory, generates a data information entry corresponding to the macroblock, and outputs the data information entry to the data information pre- Take the FIFO module;
( 2)查询、读取和替换数据信息:所述数据信息缓存控制器模块从数据信息预取 FIFO 中取出所述数据信息条目， 将该数据信息条目和数据信息缓存单元中的数据块比较， 如 果此数据信息条目对应的数据块在数据信息缓存单元中存在， 则数据信息缓存控制器模 块读取该数据块； 如果在数据信息缓存单元中只存在所述数据块中的部分数据， 则保留 重用数据， 数据信息缓存控制器模块向外部存储器发起访问取得剩下的数据， 并将所述 重用数据和剩下的数据通过移位组合成相应的数据块； 如果在数据信息缓存单元中没有 所述数据块中的任何数据， 数据信息缓存控制器模块便向外部存储器控制器发出相应的 数据信息， 并取得该数据块； 替换数据信息时， 所述数据信息缓存控制器模块依据数据 命中与否， 优先将所述数据信息缓存单元中与所述数据信息条目对应的数据块不符的数 据替换； (2) querying, reading and replacing the data information: the data information cache controller module extracts the data information item from the data information prefetch FIFO, and compares the data information item with the data block in the data information buffer unit, If the data block corresponding to the data information entry exists in the data information cache unit, the data information cache controller module reads the data block; if only part of the data in the data block exists in the data information cache unit, then Reusing data, the data information cache controller module initiates access to the external memory to obtain the remaining data, and combines the reused data and the remaining data into corresponding data blocks by shifting; if there is no data in the data information cache unit For any data in the data block, the data information cache controller module sends corresponding data information to the external memory controller, and obtains the data block; when the data information is replaced, the data information cache controller module hits according to the data. Prefer the data information buffer unit and the data letter preferentially The data block corresponding to the data entry does not match the data replacement;
( 3)发送数据信息： 所述数据信息缓存控制器将读取的数据块中的数据信息依次发 送给相应的可重构阵列； (3) transmitting data information: the data information buffer controller sequentially sends the data information in the read data block to the corresponding reconfigurable array;
(4) 重复步骤（1 ) 至步骤（3)， 直至所有数据信息条目对应的数据块都发送完毕。 有益效果： 本发明利用预先解析的宏块数据信息， 对数据缓存分为完全不命中、 部 分命中和完全不命中分开处理， 将数据进行最大程度上的重用， 减少了数据带宽的占用， 减少了对外部存储器的访问次数， 提高了大规模粗粒度可重构系统的性能。 (4) Repeat steps (1) through (3) until all data blocks corresponding to the data information items have been sent. Advantageous Effects: The present invention utilizes pre-parsed macroblock data information to divide the data cache into complete misses, partial hits, and complete misses, respectively, to maximize data reuse, reducing data bandwidth occupation, and reducing The number of accesses to external memory improves the performance of large-scale coarse-grained reconfigurable systems.
附图说明 DRAWINGS
图 1为本发明实施例所述的媒体处理可重构系统中基于预先解码分析的数据信息缓
存的结构示意图； FIG. 1 is a schematic diagram of data information based on pre-decoding analysis in a media processing reconfigurable system according to an embodiment of the present invention; Schematic diagram of the structure;
图 2为图 1中所示的媒体处理可重构系统中基于预先解码分析的数据信息缓存中的 数据缓存控制器的结构示意图； 2 is a schematic structural diagram of a data cache controller in a data information cache based on pre-decoding analysis in the media processing reconfigurable system shown in FIG. 1;
图 3为图 1所示的媒体处理可重构系统中基于预先解码分析的数据信息缓存中数据 信息预取 FIFO模块内数据信息条目的说明示意图； 3 is a schematic diagram showing an entry of data information in a data information prefetching FIFO module in a data information buffer based on pre-decoding analysis in the media processing reconfigurable system shown in FIG. 1;
图 4为图 1所示的媒体处理可重构系统中基于预先解码分析的数据信息缓存中数据 信息缓存单元内数据块的说明示意图； 4 is a schematic diagram showing the data blocks in the data information buffer unit in the data information buffer based on the pre-decoding analysis in the media processing reconfigurable system shown in FIG. 1;
图 5为本发明实施例所述的媒体处理可重构系统中基于预先解码分析的数据信息缓 存的管理方法的流程图； FIG. 5 is a flowchart of a method for managing data information cache based on pre-decoding analysis in a media processing reconfigurable system according to an embodiment of the present invention; FIG.
图 6为本发明实施例所述的媒体处理可重构系统中基于预先解码分析的数据信息缓 存的管理方法中对于更新数据缓存单元中数据块的流程图； 6 is a flowchart of updating a data block in a data buffer unit in a management method of data information cache based on pre-decoding analysis in a media processing reconfigurable system according to an embodiment of the present invention;
图 7为本发明实施例所述的媒体处理可重构系统中基于预先解码分析的数据信息缓 存结构应用连接图。 FIG. 7 is a connection diagram of an application of a data information cache structure based on pre-decoding analysis in a media processing reconfigurable system according to an embodiment of the present invention.
具体实施方式 detailed description
下面结合附图和具体实施例， 进一步阐明本发明， 应理解这些实施例仅用于说明本 发明而不用于限制本发明的范围， 在阅读了本发明之后， 本领域技术人员对本发明的各 种等价形式的修改均落于本申请所附权利要求所限定的范围。 The invention will be further clarified with reference to the drawings and specific embodiments, which are to be construed as illustrative only and not to limit the scope of the invention. Modifications of equivalent forms are intended to fall within the scope defined by the appended claims.
如图 1所示， 媒体处理可重构系统中基于预先解码分析的数据信息缓存结构， 包括流 媒体处理器模块： 用于解析从外部存储器取得的码流中的宏块， 生成处理该宏块对应的 宏块层数据信息， 并将该宏块层数据信息输出到数据信息预取 FIFO模块； 数据信息预取 FIFO模块： 用于依次存储上述流媒体处理器模块生成的数据信息条目； 数据信息缓存单 元 （简称 "数据缓存单元" ） ： 用于缓存从外部存储器中取到的数据信息块 （简称 "数 据块" ） ； 数据信息缓存控制器模块： 用于根据数据信息预取 FIFO模块中的数据信息条 目， 判断所需的数据信息是否存在于数据信息缓存单元中， 或者是部分存在于数据信息 缓存单元中， 或者完全不存在于数据信息缓存单元中。 并通过比较结果将数据信息缓存 单元中相应的数据块进行移位组合等操作形成可重构计算单元所需的数据信息块， 最后 发送至相应的可重构阵列。 As shown in FIG. 1, a data information cache structure based on pre-decoding analysis in a media processing reconfigurable system includes a streaming media processor module: configured to parse a macroblock in a code stream obtained from an external memory, and generate and process the macroblock Corresponding macroblock layer data information, and outputting the macroblock layer data information to the data information prefetching FIFO module; the data information prefetching FIFO module: for sequentially storing the data information items generated by the streaming media processor module; Cache unit (referred to as "data cache unit"): used to cache data information blocks (referred to as "data blocks") taken from external memory; data information cache controller module: used to prefetch FIFO modules based on data information The data information item determines whether the required data information exists in the data information buffer unit, or exists partially in the data information buffer unit, or does not exist in the data information buffer unit at all. And by comparing the results, the corresponding data blocks in the data information buffer unit are shifted and combined to form a data information block required by the reconfigurable computing unit, and finally sent to the corresponding reconfigurable array.
如图 2所示， 数据信息缓存控制器 （简称 "数据缓存控制器" ）模块， 包括比较， 移 位拼接及数据选择单元。 数据缓存控制器通过比较数据信息预取 FIFO模块中的条目和数 据信息缓存单元中的数据信息得出相应的命中信息， 然后将相应的控制信息发送给数据 选择单元， 移位、 拼接单元及外部存储器。 如果此条目对应的数据块在数据缓存单元中 存在， 则数据缓存控制器读取该数据块， 将其发送至可重构计算阵列； 如果只有部分命 中， 则保留重用数据， 向外部存储器发起访问取得剩下数据块， 并将两者通过移位拼接
组合成相应的数据块并且存储在数据信息缓存单元中； 如果完全不命中， 数据缓存控制 器便向外部存储器发出相应的数据信息， 取得该数据块将其发送至可重构计算阵列并存 储在数据信息缓存单元中。 As shown in FIG. 2, a data information cache controller (referred to as a "data cache controller") module includes a comparison, shift stitching, and data selection unit. The data cache controller obtains the corresponding hit information by comparing the data information pre-fetching the entry in the FIFO module with the data information in the data information buffer unit, and then transmitting the corresponding control information to the data selection unit, shifting, splicing unit and external Memory. If the data block corresponding to the entry exists in the data cache unit, the data cache controller reads the data block and sends it to the reconfigurable computing array; if there is only a partial hit, the reuse data is retained, and the access is initiated to the external memory. Get the remaining data blocks and stitch them together by shifting Synthesizing the corresponding data block and storing it in the data information buffer unit; if it is completely missed, the data cache controller sends corresponding data information to the external memory, obtains the data block and sends it to the reconfigurable computing array and stores it in Data information cache unit.
如图 3所示， 数据信息预取 FIFO模块， 包含 A个 FIFO单元， 每个 FIFO单元由包括所需 宏块的参考帧编号 P0C， 水平和垂直位置分量 （x， y) ， 实际所需宏块大小 （MXN， M代 表宏块宽度， N代表宏块的高度）这三者形成的数据信息条目 （简称"条目"）， 用 entry 表示。 As shown in FIG. 3, the data information prefetch FIFO module includes A FIFO units, each FIFO unit consists of a reference frame number P0C including a desired macroblock, horizontal and vertical position components (x, y), and actual required macros. The data size entry (referred to as "entry") formed by the three block sizes (MXN, M for the macroblock width and N for the height of the macroblock) is represented by entry.
如图 4所示， 数据信息缓存单元， 包含双向预测的前向和后向两个缓存单元， 每个缓 存单元中有 B个数据块， 一共有 2 X B个数据块。 每个缓存单元都是由具体的数据块组成。 参数 A、 B都是通过实验得出具体的数值， 使得收益率最好。 As shown in FIG. 4, the data information buffering unit includes two forward and backward buffer units of bidirectional prediction, and each of the buffer units has B data blocks, and a total of 2×B data blocks. Each cache unit is composed of specific data blocks. Parameters A and B are experimentally derived to obtain specific values, which results in the best yield.
如图 5所示， 数据信息缓存的管理方法， 生成数据信息条目： 所述流媒体处理器模块 解析从外部存储器取得的码流中的宏块， 生成处理该宏块对应的宏块层数据信息， 并将 该宏块层数据信息输出到数据信息预取 FIFO模块； 查询、 读取和替换数据信息： 如图 6所 示， 所述数据缓存控制器从数据信息预取 FIFO中取出一个条目， 将该条目中的内容与数 据缓存单元中的数据块比较， 如果此条目对应的数据块在数据缓存单元中存在， 则数据 缓存控制器读取该数据块； 如果只有部分命中， 则保留重用数据， 向外部存储器发起访 问取得剩下数据块， 并将两者通过移位组合成相应的数据块； 如果完全不命中， 数据缓 存控制器便向外部存储器控制器发出相应的数据信息， 并取得该数据块。 替换数据信息 时， 数据缓存控制器会依据数据信息预取 FIFO模块中的条目选择出数据缓存单元中接下 来一段时间不用的数据信息， 将其替换。 As shown in FIG. 5, a data information cache management method generates a data information entry: the streaming media processor module parses a macroblock in a code stream obtained from an external memory, and generates macroblock layer data information corresponding to the macroblock. And outputting the macroblock layer data information to the data information prefetch FIFO module; querying, reading and replacing the data information: as shown in FIG. 6, the data cache controller takes an entry from the data information prefetch FIFO, Comparing the content in the entry with the data block in the data cache unit, if the data block corresponding to the entry exists in the data cache unit, the data cache controller reads the data block; if only partial hits, the retained data is retained Initiating an access to the external memory to obtain the remaining data block, and combining the two into a corresponding data block by shifting; if it is completely missed, the data cache controller sends corresponding data information to the external memory controller, and obtains the data block. When the data information is replaced, the data cache controller selects the data information in the data buffer unit that is not used for a period of time according to the data information prefetching the entry in the FIFO module, and replaces it.
发送数据信息： 所述数据缓存控制器将读取的完整数据块依次发送给相应的可重构 阵列。 重复上述步骤， 直至所有数据信息条目对应的数据块都发送完毕。 Transmitting data information: The data buffer controller sequentially sends the read complete data block to the corresponding reconfigurable array. Repeat the above steps until all the data blocks corresponding to the data information items have been sent.
三个阶段的运转方式为流水线方式， 从而充分利用了数据信息缓存的资源， 提高了 大规模粗粒度可重构系统的运行效率。 The three-stage operation mode is a pipeline mode, which fully utilizes the resources of the data information cache and improves the operation efficiency of the large-scale coarse-grained reconfigurable system.
如图 7所示， H. 264协议的高清数字视频解码 (H. 264 1080p@30fps HiP@Level4) 采 用了本发明所提出的媒体处理可重构系统中基于预先解码分析的数据信息缓存结构及管 理方法， 能够实现 H. 264 1080p@30fps HiP@Level4的高清视频解码要求。 该系统的结构 包括： 用作主控器的 ARM7TDMI处理器、 数据信息缓存结构、 可重构阵列、 自定义外部存 储器访问接口、 外部存储器。 选择具有小型、 快速、 低能耗、 编译器支持好等优点的 ARM7TDMI处理器作为主控 CPU, 用于控制系统运行的调度； 数据信息缓存通过 64bit的自 定义外部存储器接口总线与外部存储器相连接， 外部存储器选用最常用的嵌入式外部存 储器 DDR SDRAM, 具有良好的性价比以及能耗比； 可重构计算单元共有两个， 每个中有 8 个可重构阵列， 每个可重构阵列均含有 8 X 8个计算单元。 对于该验证系统， 对应的流处
理器每次生成相应的数据信息条目， 数据信息条目包括三部分， 其宽度为 31bit， 参考帧 编号为 8bit， 水平和垂直分量分别为 6bit和 7bit， 宏块的宽度和高度都为 5bit。 数据信 息预取 FIFO模块包含 256个 FIFO单元， 其总大小为 IK Bytes。 数据信息缓存模块包含 32个 cache块， 每个 cache块中数据大小为 16 x 16bit。 对于验证系统， 以没有加入该数据信 息缓存结构为对比试验， 也就是直接从外部存储器中取得数据。 实验结果表明， 采用此 本发明提出的数据信息缓存结构以及相应的数据信息缓存管理方法， 系统对外部存储器 的访问次数减少 30%左右， 带宽节省 45%左右， 使得整个性能提升 40%左右。
As shown in FIG. 7, the HD digital video decoding of the H.264 protocol (H.264 1080p@30fps HiP@Level4) adopts the data information buffer structure based on the pre-decoding analysis in the media processing reconfigurable system proposed by the present invention. Management method, capable of realizing HD video decoding requirements of H.264 1080p@30fps HiP@Level4. The structure of the system includes: ARM7TDMI processor used as the master, data information cache structure, reconfigurable array, custom external memory access interface, external memory. The ARM7TDMI processor with small, fast, low power consumption, and good compiler support is selected as the main control CPU for controlling the scheduling of system operation; the data information buffer is connected to the external memory through a 64-bit custom external memory interface bus. The external memory uses the most commonly used embedded external memory DDR SDRAM, which has good cost performance and energy consumption ratio; there are two reconfigurable computing units, each with 8 reconfigurable arrays, each of which has a reconfigurable array. 8 X 8 computing units. For the verification system, the corresponding stream Each time the processor generates a corresponding data information entry, the data information entry includes three parts, the width of which is 31 bits, the reference frame number is 8 bits, the horizontal and vertical components are 6 bits and 7 bits, respectively, and the width and height of the macro block are 5 bits. The Data Information Prefetch FIFO module contains 256 FIFO units with a total size of IK Bytes. The data information cache module contains 32 cache blocks, each of which has a data size of 16 x 16 bits. For the verification system, the comparison structure is not added to the data information cache structure, that is, the data is directly obtained from the external memory. The experimental results show that with the data information cache structure and the corresponding data information cache management method proposed by the present invention, the number of accesses to the external memory by the system is reduced by about 30%, and the bandwidth is saved by about 45%, so that the overall performance is improved by about 40%.
Claims
1、 一种基于预先解码分析的数据信息缓存管理系统， 包括流媒体处理器模块、 数据 信息预取 FIFO模块、 数据信息缓存单元和数据信息缓存控制器模块； 1. A data information cache management system based on pre-decoding analysis, including a streaming media processor module, a data information prefetch FIFO module, a data information cache unit and a data information cache controller module;
所述流媒体处理器模块： 用于解析从外部存储器取得的码流中的宏块， 生成处理该 宏块对应的数据信息条目， 并将该数据信息条目输出到数据信息预取 FIFO模块； The streaming media processor module is: used to parse the macroblocks in the code stream obtained from the external memory, generate and process data information entries corresponding to the macroblocks, and output the data information entries to the data information prefetch FIFO module;
所述数据信息预取 FIFO模块： 用于依次存储所述流媒体处理器模块生成的数据信息 条目； The data information prefetch FIFO module: is used to store the data information entries generated by the streaming media processor module in sequence;
所述数据信息缓存单元： 用于缓存从外部存储器中取到的数据块； The data information cache unit: is used to cache data blocks retrieved from the external memory;
所述数据信息缓存控制器模块： 用于根据数据信息 FIFO模块中的数据信息条目， 判 断所需的数据信息是全部存在于数据信息缓存单元中， 或者是部分存在或者是全部不存 在于数据信息缓存单元中， 并根据判断结果将数据信息缓存单元中相应的数据块形成可 重构计算单元所需的数据块， 最后发送至相应的可重构阵列。 The data information cache controller module: is used to determine, based on the data information entries in the data information FIFO module, whether all the required data information exists in the data information cache unit, or part of it exists or all of it does not exist in the data information. In the cache unit, the corresponding data blocks in the data information cache unit are formed into data blocks required by the reconfigurable computing unit according to the judgment results, and finally sent to the corresponding reconfigurable array.
2、 根据权利要求 1 所述基于预先解码分析的数据信息缓存管理系统， 其特征在于： 所述数据信息预取 FIFO模块包括 A个 FIFO单元， 其中 A为不小于 1的整数， 每个所述 FIFO 单元存储一个数据信息条目， 所述数据信息条目由所需宏块的参考帧编号、 水平和 垂直位置分量与实际所需宏块大小组成。 2. The data information cache management system based on pre-decoding analysis according to claim 1, characterized in that: the data information pre-fetch FIFO module includes A FIFO units, where A is an integer not less than 1, and each of the The FIFO unit stores an entry of data information consisting of the reference frame number of the required macroblock, the horizontal and vertical position components and the actual required macroblock size.
3、 根据权利要求 1 所述基于预先解码分析的数据信息缓存管理系统， 其特征在于： 所述数据信息缓存单元包含应用双向预测的前向和后向两个缓存单元， 分别存储前向预 测和后向预测参考帧数据， 每个所述缓存单元中有 B个数据块， 一共有 2 X B个数据块。 3. The data information cache management system based on pre-decoding analysis according to claim 1, characterized in that: the data information cache unit includes two forward and backward cache units applying bidirectional prediction, respectively storing forward prediction and For backward prediction reference frame data, there are B data blocks in each buffer unit, and there are 2×B data blocks in total.
4、 根据权利要求 1 所述基于预先解码分析的数据信息缓存管理系统， 其特征在于： 所述数据信息缓存控制器模块包括数据信息比较单元， 数据选择器和数据移位、 拼接单 元； 所述数据信息比较单元用于比较数据信息预取 FIFO模块中的数据信息条目和数据信 息缓存单元中的数据块， 如果此数据信息条目对应的数据块在数据信息缓存单元中存 在， 则数据信息比较单元读取该数据块； 如果在数据信息缓存单元中只存在所述数据块 中的部分数据或没有所述数据块中的任何数据， 则将相应的命中信息发送给数据选择 器； 数据选择器根据部分命中或者完全不命中信息选择将从所述外部存储器取得的数据 发送给移位、 拼接单元或者直接发送给数据信息缓存单元； 数据移位、 拼接单元， 在数 据部分命中时， 将部分命中的数据和从外部存储器取得的剩余数据拼接成可重构阵列所 需数据块。 4. The data information cache management system based on pre-decoding analysis according to claim 1, characterized in that: the data information cache controller module includes a data information comparison unit, a data selector and a data shifting and splicing unit; The data comparison unit is used to compare the data entry in the data prefetch FIFO module and the data block in the data cache unit. If the data block corresponding to this data entry exists in the data cache unit, the data comparison unit Read the data block; If only part of the data in the data block or no data in the data block exists in the data information cache unit, then the corresponding hit information is sent to the data selector; The data selector is based on The partial hit or complete miss information selection will send the data obtained from the external memory to the shifting and splicing unit or directly to the data information cache unit; the data shifting and splicing unit, when the data is partially hit, will partially hit the data. The data and the remaining data obtained from the external memory are spliced into the data blocks required by the reconfigurable array.
5、 一种利用如权利要求 1 所述基于预先解码分析的数据信息缓存管理系统的管理方
法， 包括如下步骤： 5. A management method using the data information cache management system based on pre-decoding analysis as claimed in claim 1 method, including the following steps:
( 1 ) 生成数据信息条目： 所述流媒体处理器模块解析从外部存储器取得的码流中的 宏块， 生成处理该宏块对应的数据信息条目， 并将该数据信息条目输出到数据信息预取 (1) Generate data information entries: The streaming media processor module parses the macroblocks in the code stream obtained from the external memory, generates and processes the data information entries corresponding to the macroblocks, and outputs the data information entries to the data information pre-processor. Pick
FIFO模块； FIFO module;
( 2 ) 查询、 读取和替换数据信息： 所述数据信息缓存控制器模块从数据信息预取 FIFO 中取出所述数据信息条目， 将该数据信息条目和数据信息缓存单元中的数据块比 较， 如果此数据信息条目对应的数据块在数据信息缓存单元中存在， 则数据信息缓存控 制器模块读取该数据块； 如果在数据信息缓存单元中只存在所述数据块中的部分数据， 则保留重用数据， 数据信息缓存控制器模块向外部存储器发起访问取得剩下的数据， 并 将所述重用数据和剩下的数据通过移位组合成相应的数据块； 如果在数据信息缓存单元 中没有所述数据块中的任何数据， 数据信息缓存控制器模块便向外部存储器控制器发出 相应的数据信息， 并取得该数据块； 替换数据信息时， 所述数据信息缓存控制器模块依 据数据命中与否， 优先将所述数据信息缓存单元中与所述数据信息条目对应的数据块不 符的数据替换； (2) Query, read and replace data information: The data information cache controller module retrieves the data information entry from the data information prefetch FIFO, compares the data information entry with the data block in the data information cache unit, If the data block corresponding to this data entry exists in the data cache unit, the data cache controller module reads the data block; if only part of the data in the data block exists in the data cache unit, it is retained. To reuse the data, the data information cache controller module initiates access to the external memory to obtain the remaining data, and combines the reused data and the remaining data into corresponding data blocks through shifting; if there is no such data in the data information cache unit, Any data in the data block, the data cache controller module sends the corresponding data information to the external memory controller and obtains the data block; when replacing the data information, the data cache controller module determines whether the data is hit or not. , give priority to replacing the data in the data information cache unit that is inconsistent with the data block corresponding to the data information entry;
( 3 ) 发送数据信息： 所述数据信息缓存控制器将读取的数据块中的数据信息依次发 送给相应的可重构阵列； (3) Sending data information: The data information cache controller sends the data information in the read data blocks to the corresponding reconfigurable array in sequence;
( 4 ) 重复步骤 （1 ) 至步骤 （3 )， 直至所有数据信息条目对应的数据块都发送完 毕。
(4) Repeat steps (1) to (3) until the data blocks corresponding to all data information entries have been sent.
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