WO2014102800A1

WO2014102800A1 - Method and device for reliable storage in nor flash memory

Info

Publication number: WO2014102800A1
Application number: PCT/IL2013/051087
Authority: WO
Inventors: Simon Litsyn
Original assignee: Ramot At Tel-Aviv University Ltd.
Priority date: 2012-12-30
Filing date: 2013-12-30
Publication date: 2014-07-03

Abstract

A method and device for securely storing and reading out data in a flash memory device using multi-level voltage cells uses redundancy based error correction to correct the multi-bit voltage level readings. A number of voltage levels per cell is provided which is higher (typically by one or two) than the number needed for the data to be stored. The resulting redundancy is used to correct the cell readings, for example by correcting the weakest cell level reading in a readout vector until an allowable readout vector is achieved.

Description

METHOD AND DEVICE FOR RELIABLE STORAGE IN NOR FLASH MEMORY FIELD AND BACKGROUND OF THE INVENTION

The present invention, in some embodiments thereof, relates to a method and device for reliable storage in NOR flash memory, and more particularly but not exclusively, to error detection and optionally error correction in NOR MLC (multi-level cell) technology.

Flash memory is a solid-state non-volatile data storage device that can be electronically erased and re-written. There are two main types of flash, based on the NAND and NOR logic gates, and the individual flash memory cells show the characteristics of the corresponding gates.

NAND type flash is generally written to, read and erased in pages or blocks containing relatively large amounts of information. In contrast thereto, NOR type flash is written to and read in small groups of cells, storing, for example, one bit, or one or two bytes of information.

Multi-level cell technology uses multiple voltage levels per cell to allow the storage of more than a single bit. Conventional SLC - single level cell - technology, allows each cell to store either a '0' or a T and thus the information capacity is one bit per cell. MLC technology provides multiple voltage levels per cell. For example, if three defined voltage levels are allowed together with the zero state, then binary values, 00, 01, 10 and 11 can each be assigned a unique voltage level, allowing for effective storage of two bits per cell. The cost, however, is that the margin between distinct levels is smaller, increasing the likelihood of errors. On the other hand, the primary benefit of MLC flash memory is its lower cost per unit of storage and a higher data density.

The main distinction between NOR and NAND flash memory is that NOR memory allows writing into and reading from a small number of cells. Commonly, the granularity level of storage is either a single bit, or single byte = 8 bits of information. Moreover, MLC (multi-level cell) technology, allowing storage of more than one bit per cell, is now beginning to dominate in current memory devices, the most popular of them using four voltage levels for information storage. In such devices, one cell can store two bits in the four level example described above, so that four memory cells are all that are needed to store one byte of information. The requirements for the reliability of information stored in flash memories are very high: the allowed bit error rate in such devices lies in the range 10 -^"12 to 10 -^"15. To achieve such reliability in NAND flash memory an error correcting code can be used, however, to be efficient it has to employ a significant amount of information (usually thousands or tens of thousands of bits) in each encoding.

An example of an error correction system for multi-level memory cells is US Patent 6,530,058 to Visconti, filed 24^th February 2000.

Now in NOR memories the numbers of bits written are much smaller, and error correction, such as exemplified by Visconti, becomes very inefficient when protecting small amounts of data as independent units. The uncorrected error rates in either type of memory lie between 10 -^"1 and 10 -^"3 , which in current NAND memories are corrected to the required output level. This is not the case for NOR memories, where no correction is used.

The same issue applies to Phase Change Memory (PCM) which is made of both NAND and NOR gates, and to which, again, small amounts of data are often written.

SUMMARY OF THE INVENTION

The present embodiments apply error detection/correction to MLC technology in NOR flash and to PCM technology. The present embodiments may further provide error detection/correction to MLC technology in general based on providing an additional voltage level to the cells to provide redundancy, and to provide the additional voltage level to NOR flash in particular.

The present embodiments may provide a method and device for securely storing and reading out data in a NOR or PCM non-volatile memory device or flash memory device using multi-level voltage cells by using redundancy based error correction to correct the multi-bit voltage level readings. A number of voltage levels per cell is provided which is higher (typically by one or two) than the number needed for the data to be stored. Parity check bits are not used, but rather all of the states store actual data. Nevertheless the redundancy is used to set a distance between allowable vectors and thus to correct the cell readings. The distance provides an indication about the most probable correct state, the smaller the distance is, the more probable is the state. However voltage level measurement can reveal which of the level readings in the vector is the most marginal reading, and that reading may be corrected. As the embodiments rely on distance between allowable vectors rather than on dedicated error correction bits, it makes no difference to the efficiency whether the data read write size is a few bits or multiple kilobytes.

According to an aspect of some embodiments of the present invention there is provided a memory device for storage of data, comprising:

multi-level voltage cells each cell capable of assuming two or more states for storing a plurality of bits of the data;

a readout unit for reading the cells, extracting the states and translating the states into corresponding bits;

a write unit for writing the data as allowable vectors into the multi-level voltage cells, the allowable vectors being a subset of a larger set of total vectors; and

an error control unit configured for redundancy-based error detection and correction of the data, wherein the multi-level voltage cells are configured with a first number of voltage levels sufficient for a first number of bits to define the allowable vectors, and further with at least one additional voltage level to include the set of total vectors, and provide a predefined distance between each of the allowable vectors for the redundancy-based error detection or correction, the error control unit being configured to detect non-allowable vectors and correct the non-allowable vectors to a nearest one of the allowable vectors.

In an embodiment, the readout unit is configured to read out each cell on the basis of proximity to a defined voltage level, and the error control unit is configured to obtain a reliability of a respective reading being based on proximity to the defined voltage level.

In an embodiment, upon detection of a non-allowable vector, the error control unit is configured to find a least reliable cell reading and to correct the least reliable cell reading to a nearest alternative cell reading to determine the nearest allowable vector.

In an embodiment, the write unit and the readout unit are configured to write or read data respectively in individual bytes or individual words.

The device may be a NOR-based memory device, or a phase change memory (PCM) device, or for that matter a NAND based device. In an embodiment, the providing a predefined distance between each of the allowable vectors comprises spacing the allowable vectors over a space defined by the first number of voltage levels combined with the at least one additional voltage level.

The predefined distance may be a Hamming distance, or its discrete cousin a Manhattan distance.

According to a second aspect of the present invention there is provided a memory device for storage of data, comprising:

an error control unit configured for redundancy-based error detection and correction of the data, wherein the multi-level voltage cells are configured with a first number of voltage levels sufficient for a first number of bits to define the allowable vectors, and further with at least one additional voltage level to include the set of total vectors, wherein the readout unit is configured to read out each cell on the basis of proximity to a defined voltage level, and the error control unit is configured to obtain a reliability of a respective reading being based on proximity of the readout to the defined voltage level wherein, upon detection of a non-allowable vector, the error control unit is configured to find a least reliable cell reading and to correct the least reliable cell reading to a nearest alternative cell reading to determine the nearest allowable vector.

According to a third aspect of the present invention there is provided a method of securely storing and reading out data in a memory device, including a flash memory device or other kind of non-volatile memory device comprising multi-level voltage cells, the method comprising:

defining a first number of voltage levels per cell sufficient to store a predetermined amount of data in the device;

providing a second number of voltage levels per cell, the second number being higher than the first number; storing the data as a set of allowable vectors, the allowable vectors fitting within a space defined by the first number;

spreading the set of allowable vectors over a second space defined by the second number, to provide a distance between each allowable vector;

reading out vectors from the flash memory;

testing each vector to determine whether it is an allowable vector; and correcting any non-allowable vector to a nearest allowable vector.

The method may comprise reading out the data on the basis of proximity of a voltage at each cell to a defined voltage level, and determining a strength of reading at each cell according to the respective proximity.

Correcting to a nearest allowable vector may involve finding and correcting a least strong cell reading to a nearest available alternative reading.

According to a fourth aspect of the present invention there is provided a memory device for storage of data, the device including a non-volatile memory device including flash memory, the device comprising multi-level voltage cells each cell storing a plurality of bits of the data as a stored voltage level, the multi-level voltage cells having a first number of levels M, the first number being greater than a second number N, the first number being a number of levels providing a set of total vectors, the second number being a number of levels required for non-redundant storage of the data as a set of allowable vectors, the set of allowable vectors fitting as a subset into the set of total vectors, the allowable vectors being those vectors whose data satisfy an equality or a system of equalities modulo a predetermined number.

In an embodiment, the second number N is a number different from the predetermined number, and/or the first number M is one greater than the second number M.

Unless otherwise defined, all technical and/or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention pertains. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of embodiments of the invention, exemplary methods and/or materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting. Implementation of the method and/or system of embodiments of the invention can involve performing or completing selected tasks manually, automatically, or a combination thereof. Moreover, according to actual instrumentation and equipment of embodiments of the method and/or system of the invention, several selected tasks could be implemented by hardware, by software or by firmware or by a combination thereof using an operating system.

For example, hardware for performing selected tasks according to embodiments of the invention could be implemented as a chip or a circuit. As software, selected tasks according to embodiments of the invention could be implemented as a plurality of software instructions being executed by a computer using any suitable operating system. In an exemplary embodiment of the invention, one or more tasks according to exemplary embodiments of method and/or system as described herein are performed by a data processor, such as a computing platform for executing a plurality of instructions. The data processor may include a volatile memory for storing instructions and/or data and/or a non- volatile storage, for example, a magnetic hard-disk, flash memory and/or removable media, for storing instructions and/or data. A network connection may be provided and a display and/or a user input device such as a keyboard or mouse may be available as necessary. BRIEF DESCRIPTION OF THE DRAWINGS

Some embodiments of the invention are herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments of the invention. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments of the invention may be practiced.

In the drawings:

FIG. 1 is a schematic diagram of a prior art cross section of NOR flash memory cells of an array;

FIG. 2 is a simplified block diagram illustrating NOR or PCM or other nonvolatile memory MLC cells with error detection or correction according to an embodiment of the present invention; FIG. 3 is a simplified diagram illustrating defined voltage levels in a NOR or PCM or other non-volatile memory MLC cell and illustrating strong a) and weak b) readouts;

FIG. 4 is a simplified flow chart illustrating a procedure for cell readout with error correction based on strong and weak cell readings from a non- volatile memory cell including NOR, PCM, and flash, according to an embodiment of the present invention; and

FIG. 5 is a simplified flow chart showing a variation of the procedure of Fig. 4 for the case where allowable vectors are defined by their division modulo 2.

DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

The present invention, in some embodiments thereof, relates to a method and device for reliable storage in NOR or PCM or other non-volatile memory including flash memory, and more particularly but not exclusively to error detection and optionally error correction in NOR or PCM or other non-volatile memory MLC (multilevel cell) technology.

A method and device for securely storing and reading out data in a NOR or PCM or other non-volatile memory or flash memory device using multi-level voltage cells uses redundancy based error correction to correct the multi-bit voltage level readings. A number of voltage levels per cell is provided which is higher (typically by one) than the number needed for the data to be stored. The resulting redundancy allows allowable vectors to be distributed over a larger space so that there is a distance between each allowable vector. That distance can then be used to identify unallowable vectors and enable their correction into allowable vectors. Readings are of voltage levels in the cells, and some of the readings will be closer to the predefined levels than others, allowing readings to be rated as strong or weak readings. Then the weakest reading in a non-allowable vector can be corrected into the nearest allowable vector. Hereafter references to NOR memory are to be construed as references to NOR or PCM or other non-volatile memory including flash memory.

In multi-level NOR flash memory, a single cell reading represents multiple bits.

The present embodiments provide an error detection and/or correction device and method based on the cell readings even though the cell readings are not the equivalent of the bits being read in conventional data storage systems.

An embodiment involves increasing the number of recognized voltage levels beyond that needed for the declared data capacity of the device. The resulting redundancy can be used to recover the original data following errors introduced by the storage. Numerous techniques for error correction and recovery are known to those skilled in the field of information theory based on the available redundancy and the present disclosure gives only exemplary techniques for using the redundancy.

Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the following description and/or illustrated in the drawings and/or the Examples. The invention is capable of other embodiments or of being practiced or carried out in various ways.

Referring now to the drawings, Figure 1 is a schematic drawing of some cells of the known NOR flash memory device 10. The device stores data in a manner suggestive of a basic NOR gate. The figure is a cross-section of an array in which a series of word lines 12 extend into the depth of the image and a bit line 14 allows for access of individual bits. The cells that store the data are the transistors 16. In the case of MLC technology, the individual transistors 16 do not store individual bits but rather store a voltage level which is one of a set of predefined voltage levels defining two or more bits, so that the bit line 14 actually reads out the voltage level which then needs to be interpreted to recover the individual bits.

Reference is now made to Figure 2, which is a simplified diagram showing a NOR flash memory device 20 according to an embodiment of the present invention. The device includes one or more arrays 22 of MLC cells, a writing unit 24, a reading unit 26 and an error detection or correction unit 28. Storage of data in the device takes place over the multi-level voltage cells, each cell storing multiple bits of the data. The error detection/correction unit 24 carries out redundancy-based error detection and/or correction of the data in the event of errors.

Reference is now made to Fig. 3 which shows a set of five defined voltage levels and two readouts a) and b) based on the voltage levels. The multi-level voltage cells have a series of defined voltage levels each indicating the settings for a group of bits. Thus for four voltage levels 0 - 3, two bits can be set to store 2 values, and for five voltage levels, an extra bit can be set. Two bits (and the corresponding four voltage levels) may be sufficient for the declared data size, but additional voltage levels, typically one extra voltage level, is added to provide redundancy for the redundancy- based error detection or correction.

The information is thus stored in a set of cells having a number of levels M greater than the number required for non-redundant storage. Thus for example, four cells with four levels is substituted by four cells with five or six levels, where the levels are enumerated by the numbers from 0 to M-l, and the allowed storage combinations are a subset of the total storage combinations. The members of the subset satisfy an equality or a system of equalities modulo a prescribed number. For example the allowed storage combinations are those of the total possible vectors in which the sum of the stored values equals 1 modulo 2. If the combination does not satisfy 1 modulo 2 then the combination is not allowed and it is assumed that an error has occurred. The error correction system responds by looking for the lowest confidence readout and changes it, as shown in Fig 3 and described as follows.

Two readouts are shown in Fig. 3, a strong readout in a) and a weak readout in b). The readout in a) is strong because the readout is very close to the actual defined level 4 and therefore the bit pattern corresponding to level 4 may be read with high confidence. The readout in b) is not much closer to 4 than it is to 3 and thus can only be read as the bit pattern corresponding to level 4 with low confidence. In the event of doubt with the final readout, b) would be a prime candidate for recognizing as a potential error and correcting to the bit pattern represented by level 3.

In general, in redundancy based schemes, there are allowable outcomes and forbidden outcomes, with the allowable outcomes dispersed amongst the forbidden outcomes so that there is a recognizable distance between any nearest two allowable outcomes. Thus, in the event of a readout result not being among the allowable readout results, the error control unit finds the weakest cell reading to correct in the hope of achieving an allowable readout result. There are numerous schemes known in the art for encoding the data to disperse allowable outcomes amongst forbidden outcomes and there are numerous schemes for making the most appropriate corrections afterwards. It is noted that in many cases, the stored data unit gives a correct result when tested for the presence of an error. Thus a check of the actual voltage levels is not required. Considerable processing power can thus be saved by only checking the voltage levels for a weakest reading after determining that the current data unit is in error.

Reference is now made to Fig. 4, which is a simplified flow diagram illustrating a method of reading out securely stored data in a NOR flash memory device comprising multi-level voltage cells, according to an embodiment of the present invention.

As explained above, the device defines a first number of voltage levels per cell sufficient to store the specified amount of data in the device, for example the first four voltage levels in Fig. 3 which are needed to store two bits per cell. An additional level is then added to provide for redundancy and the data is encoded to ensure a minimal distance between allowable codes.

With data encoded using such a system the cells are read out 30. In box 32 the cells are tested against the modulus test to find out if they form an allowable vector and if so the vector is read out and the process terminates 34.

If on the other hand the vector is not among the allowable vectors then the voltage levels of the individual cells are tested 36. The weakest cell readout is changed to its next nearest reading result 38, and the vector is tested again for allowability until an allowable vector is achieved.

Reference is now made to Fig. 5, which is a variation of Fig. 4 showing the specific case in which the test is modulo 2.

With data encoded as above the cells are read out 30. In box 32 the cells are tested modulo 2 to find out if they form an allowable vector and if so the vector is read out and the process terminates 34.

If on the other hand the vector is not among the allowable vectors then the voltage levels of the individual cells are tested 36. The weakest cell readout is changed to its next nearest reading result 38, In this case, each allowable vector is immediately adjacent a non-allowable vector and vice versa and a single change to any non- allowable vector immediately results in an allowable vector, just as adding or subtracting 1 from any odd number necessarily leaves an even number. Thus no further test is required and the corrected vector is read out 34.

The embodiments are now considered in greater detail. The described problem is approached by increasing the number of levels, in general, to a number not being a power of 2, and using a transformation of the information to be stored into a sequence of allowed voltage levels, where not all the possible combinations of voltages are used. As an example, one may store 8 bits of information in 4 memory cells each having 5 allowed voltage levels, as shown in Fig. 3. In this case, only 256 out of possible 625=5⁴ states are used, and the rest provide the redundancy. It is noted however that all states that are used are in fact storing data, and there are no separate test bits.

The general setting is as follows. Let us have n cells of M levels 0,1,...,M-1, each, where M>4. We pick 4" states out of Mⁿ possibilities using one of the methods described below. Denote all the possible combinations as

c(l), c(2),...,c(4"),

where c(i)=(c(l,i),...,c(n,i)) is an n-dimensional vector. Let the actual voltages of the stored vector be y=(vl,...,vn). Then the following decision procedure is undertaken:

Find i such that c(i) is the closest allowed sequence to v -

where k >0 is an integer number. The choice of k depends on the distribution of the distortions in the cell. It can be chosen to be k=i when the distribution is exponential - this being the most common model confirmed by measurements.

Another decision strategy is first to make individual decisions about each yj, j=l,...,n. I.e. we first transform (vl,...,vn) into l=(ll,...,ln), where Ij is the closest number to vj in the set (0,1,..,M-1 ). Then, we check if / is a legal sequence. If yes, the output is /, and if not we read v with high precision and then employ an optimal or suboptimal algorithm to find the closest legal vector to v. Some examples of such algorithms are given below. Example 1. n=4, M=5

Choose as legal sequences c=(cl,..,cn) all those satisfying cl+c2+c3+c4=a (mod 2) ( 1 )

ci £(0,1,2,3,4,5), j=l,2,3,4; where a is chosen to be either 0 or 1, such that the set of legal sequences contains at least 256 items. This is indeed possible since 625/2>256.

The decision procedure is as shown in Fig. 5 and proceeds as follows:

1. Find the closest levels to each component vj, j=l,...,n.

2. Check if they satisfy (1). If yes, output the vector.

3. If not, read the stored vector including the precision levels or strength of each cell and find the least reliable component.

4. Change the least reliable component to the second closest value of the defined voltage levels and output the resulting vector.

For the exponential distribution this method provides a decrease in the error rate from 10^"10 to 10^"12.

Example 2. n=4, M=6 cl+c2+c3+c4=a (mod 5)

(21 ci W,l,2,3,4,5), i=l,2,3,4 Example 3. n=4, M=l cl+c2+c3=a (mod 3)

cl+2c2+c4=b (mod 3)

ill ci 00,1,2,3,4,5), i=l,2,3,4

where a and b are chosen in such a way that the size of the set of legal sequences is at least 256. This is possible since 7 4 /32 =266.7>256. Example4. n=4, =8 cl=c2=c3=c4=a (mod 2)

cr+c2 '+c3 '+c4'=b (mod 2)

(41 ci (0,l,2,3,4,5), i=l,2,3,4

where cj' is the second least significant bit in the binary representation o/cj, and a and b are chosen in such a way that the size of the set of legal sequences is at least 256. This is possible since 2¹²/2⁴=256.

In all the above examples the increase in the number of levels yields a decrease in the error rate by between two and five orders of magnitude in comparison with the conventional four level byte storage without significant increase in complexity and no extra redundancy.

In the general case, the set of legal sequences can be chosen as an intersection of an affine shift of a Euclidean integer lattice with the n-dimensional cube with the side size of M- 1.

Multilevel construction

In the following, we describe a general construction which contains the previous embodiments as particular cases.

Let us have n cells with r≤ 2^m levels. Every stored value can thus be written as a vector

c⁼ (^co> ^ci>^■■■ ' ^cn-l)'

where each component c takes on a possible value from 0 to r-1. Let us present each component in binary representation, namely,

₌ ( 0 1 - 1 Λ when

c e {0,l}, i = 0, ... , n - l, 7 = 0, ... , m - 1, and

Cj = c * 2° +

* 2¹ + - + c™^"1 * 2^m"1

Now, let us have m binary error-correcting codes C_k, k = 0, ... , m— 1, with parameters (n, _fc), i.e. of length n, and with _fc code words. The combinations c to be stored are defined as follows

(c£, cf, ... , c^_i) £ C_fc, / = 0, ... , m - 1, and

0 ≤ c; ≤ r - 1

i.e. the corresponding components of the binary representations of the values in all the cells belong to a code corresponding to this component.

In one of the embodiments the minimum distances of the codes C_k, k = 0, ... , m— 1, are 2^m~k.

It is possible to estimate the number of legal vectors to be stored by averaging over all the possible cosets of the codes C_k, k = 0, ... , m— 1. This will give the following estimate

Clearly any subset of the chosen set can be used for storage. E.g. one may choose any collection of size being a power of 2.

Example. Let m = 1 and C₀ be the parity-check code of length n=4, i.e. ₀ = 8. Then for r=5 we obtain the previously described storage code with M=256.

Example. Let m = 2, n = 8, C₀ = (8,20) code with the minimum Hamming distance 3 and C_x = (8,128) parity-check code, then for r=3 we have a storage code with M=256.

In one of the embodiments decoding of the multilevel code is done by successive decoding of the component codes C_k, k = 0, ... , m— 1.

It is expected that during the life of a patent maturing from this application many relevant pulse shaping and symbol decoding technologies will be developed and the scope of the corresponding terms in the present description are intended to include all such new technologies a priori. As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise.

It is appreciated that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or as suitable in any other described embodiment of the invention. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

Although the invention has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.

All publications, patents and patent applications mentioned in this specification are herein incorporated in their entirety by reference into the specification, to the same extent as if each individual publication, patent or patent application was specifically and individually indicated to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present invention. To the extent that section headings are used, they should not be construed as necessarily limiting.

Claims

WHAT IS CLAIMED IS:

1. A non- volatile memory device for storage of data, comprising:

multi-level voltage cells each cell capable of assuming two or more states for storing a plurality of bits of said data;

a readout unit for reading said cells, extracting said states and translating said states into corresponding bits;

a write unit for writing said data as allowable vectors into said multi-level voltage cells, said allowable vectors being a subset of a larger set of total vectors; and an error control unit configured for redundancy-based error detection and correction of said data, wherein said multi-level voltage cells are configured with a first number of voltage levels sufficient for a first number of bits to define said allowable vectors, and further with at least one additional voltage level to include said set of total vectors, and provide a predefined distance between each of said allowable vectors for said redundancy-based error detection or correction, said error control unit being configured to detect non-allowable vectors and correct said non-allowable vectors to a nearest one of said allowable vectors.

2. The device of claim 1, wherein said readout unit is configured to read out each cell on the basis of proximity to a defined voltage level, and said error control unit is configured to obtain a reliability of a respective reading being based on proximity to said defined voltage level.

3. The device of claim 2, wherein, upon detection of a non-allowable vector, said error control unit is configured to find a least reliable cell reading and to correct said least reliable cell reading to a nearest alternative cell reading to determine said nearest allowable vector.

4. The device of claim 1, 2 or 3, wherein said write unit and said readout unit are configured to write or read data respectively in individual bytes or individual words.

5. The device of any preceding claim, being a NOR-based memory device.

6. The device of any one of claims 1 to 5, being a phase change memory (PCM) device.

7. The device of any preceding claims, wherein said providing a predefined distance between each of said allowable vectors comprises spacing said allowable vectors over a space defined by said first number of voltage levels combined with said at least one additional voltage level.

8. The device of any one of the preceding claims wherein said predefined distance is one member of the group consisting of a Hamming distance and a Manhattan distance.

9. A non-volatile memory device for storage of data, comprising:

a write unit for writing said data as allowable vectors into said multi-level voltage cells, said allowable vectors being a subset of a larger set of total vectors; and an error control unit configured for redundancy-based error detection and correction of said data, wherein said multi-level voltage cells are configured with a first number of voltage levels sufficient for a first number of bits to define said allowable vectors, and further with at least one additional voltage level to include said set of total vectors, wherein said readout unit is configured to read out each cell on the basis of proximity to a defined voltage level, and said error control unit is configured to obtain a reliability of a respective reading being based on proximity of said readout to said defined voltage level wherein, upon detection of a non-allowable vector, said error control unit is configured to find a least reliable cell reading and to correct said least reliable cell reading to a nearest alternative cell reading to determine said nearest allowable vector.

10. A method of securely storing and reading out data in a non- volatile memory device the device comprising multi-level voltage cells, the method comprising: defining a first number of voltage levels per cell sufficient to store a predetermined amount of data in said device;

providing a second number of voltage levels per cell, said second number being higher than said first number;

storing said data as a set of allowable vectors, said allowable vectors fitting within a space defined by said first number;

spreading said set of allowable vectors over a second space defined by said second number, to provide a distance between each allowable vector;

reading out vectors from said flash memory;

11. The method of claim 10, comprising reading out said data on the basis of proximity of a voltage at each cell to a defined voltage level, and determining a strength of reading at each cell according to said respective proximity.

12. The method of claim 11, wherein said correcting to a nearest allowable vector comprises finding and correcting a least strong cell reading to a nearest available alternative reading.

13. A non- volatile memory device for storage of data, the device comprising multi-level voltage cells each cell storing a plurality of bits of said data as a stored voltage level, said multi-level voltage cells having a first number of levels M, said first number being greater than a second number N, said first number being a number of levels providing a set of total vectors, said second number being a number of levels required for non-redundant storage of the data as a set of allowable vectors, said set of allowable vectors fitting as a subset into said set of total vectors, said allowable vectors being those vectors whose data satisfy an equality or a system of equalities modulo a predetermined number.

14. The non-volatile memory device of claim 13, wherein said second number N is a number different from said predetermined number.

15. The non- volatile memory device of claim 13, wherein said first number M is one greater than said second number M.