WO2014150516A3 - System and method to reduce read latency of a data storage device - Google Patents

System and method to reduce read latency of a data storage device Download PDF

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Publication number
WO2014150516A3
WO2014150516A3 PCT/US2014/023475 US2014023475W WO2014150516A3 WO 2014150516 A3 WO2014150516 A3 WO 2014150516A3 US 2014023475 W US2014023475 W US 2014023475W WO 2014150516 A3 WO2014150516 A3 WO 2014150516A3
Authority
WO
WIPO (PCT)
Prior art keywords
representation
controller
storage device
data storage
retrieve
Prior art date
Application number
PCT/US2014/023475
Other languages
French (fr)
Other versions
WO2014150516A2 (en
Inventor
Eran Sharon
Idan Alrod
Original Assignee
Sandisk Technologies Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Technologies Inc. filed Critical Sandisk Technologies Inc.
Priority to CN201480008994.XA priority Critical patent/CN104995607B/en
Publication of WO2014150516A2 publication Critical patent/WO2014150516A2/en
Publication of WO2014150516A3 publication Critical patent/WO2014150516A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Abstract

A data storage device includes a memory and a controller. The controller is configured to receive a read request that indicates a logical address. The controller is further configured to perform a first read operation to retrieve a representation of an entry of a logical mapping table from the memory, and perform a second read operation to retrieve a representation of a codeword from the memory. The controller is further configured to decode the representation of the codeword to determine whether an error exists at the entry, and, prior to completion of decoding, to initiate a third read operation to retrieve first read data from a first physical address corresponding to the logical address as determined based on the representation of the entry.
PCT/US2014/023475 2013-03-15 2014-03-11 System and method to reduce read latency of a data storage device WO2014150516A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201480008994.XA CN104995607B (en) 2013-03-15 2014-03-11 The system and method for reducing the reading delay of data container device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/838,662 US9116824B2 (en) 2013-03-15 2013-03-15 System and method to reduce read latency of a data storage device
US13/838,662 2013-03-15

Publications (2)

Publication Number Publication Date
WO2014150516A2 WO2014150516A2 (en) 2014-09-25
WO2014150516A3 true WO2014150516A3 (en) 2014-12-04

Family

ID=50397332

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2014/023475 WO2014150516A2 (en) 2013-03-15 2014-03-11 System and method to reduce read latency of a data storage device

Country Status (4)

Country Link
US (1) US9116824B2 (en)
CN (1) CN104995607B (en)
TW (1) TWI613675B (en)
WO (1) WO2014150516A2 (en)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160162416A1 (en) * 2014-12-08 2016-06-09 Intel Corporation Apparatus and Method for Reducing Latency Between Host and a Storage Device
US9613691B2 (en) * 2015-03-27 2017-04-04 Intel Corporation Apparatus and method for drift cancellation in a memory
US9985655B2 (en) 2015-09-01 2018-05-29 International Business Machines Corporation Generating ECC values for byte-write capable registers
US10176038B2 (en) 2015-09-01 2019-01-08 International Business Machines Corporation Partial ECC mechanism for a byte-write capable register
US9766975B2 (en) * 2015-09-01 2017-09-19 International Business Machines Corporation Partial ECC handling for a byte-write capable register
CN106547480B (en) * 2015-09-17 2019-04-12 慧荣科技股份有限公司 Data storage device and data reading method thereof
TWI615771B (en) * 2015-09-17 2018-02-21 慧榮科技股份有限公司 Data storage device and data reading method thereof
US20170141878A1 (en) * 2015-11-16 2017-05-18 Western Digital Technologies, Inc. Systems and methods for sending data from non-volatile solid state devices before error correction
TWI603335B (en) * 2016-10-19 2017-10-21 合肥兆芯電子有限公司 Mapping table loading method, memory control circuit unit and memory storage apparatus
JP2018156556A (en) 2017-03-21 2018-10-04 東芝メモリ株式会社 Computer system and memory device
US10630424B2 (en) 2017-06-30 2020-04-21 Silicon Motion, Inc. Methods for reducing data errors in transceiving of a flash storage interface and apparatuses using the same
CN109213436B (en) 2017-06-30 2021-08-24 慧荣科技股份有限公司 Method and apparatus for reducing errors in data transmission and reception in flash memory interface
US10848263B2 (en) 2017-06-30 2020-11-24 Silicon Motion, Inc. Methods for reducing data errors in transceiving of a flash storage interface and apparatuses using the same
TWI645298B (en) 2017-06-30 2018-12-21 慧榮科技股份有限公司 Methods for reducing data error in transceiving of flash storage interface and apparatuses using the same
US10637509B2 (en) 2017-06-30 2020-04-28 Silicon Motion, Inc. Methods for reducing data errors in transceiving of a flash storage interface and apparatuses using the same
KR102421149B1 (en) * 2018-01-02 2022-07-14 에스케이하이닉스 주식회사 Memory system and operating method thereof
KR20200104601A (en) 2019-02-27 2020-09-04 에스케이하이닉스 주식회사 Controller, memory sysytem and operating method thereof
KR102456173B1 (en) 2017-10-27 2022-10-18 에스케이하이닉스 주식회사 Memory system and operating method thereof
US10565051B2 (en) * 2018-02-06 2020-02-18 Alibaba Group Holding Limited Accommodating variable page sizes in solid-state drives using customized error correction
KR102456176B1 (en) 2020-05-21 2022-10-19 에스케이하이닉스 주식회사 Memory controller and operating method thereof
US11573891B2 (en) 2019-11-25 2023-02-07 SK Hynix Inc. Memory controller for scheduling commands based on response for receiving write command, storage device including the memory controller, and operating method of the memory controller and the storage device
KR102495910B1 (en) 2020-04-13 2023-02-06 에스케이하이닉스 주식회사 Storage device and operating method thereof
US11755476B2 (en) 2020-04-13 2023-09-12 SK Hynix Inc. Memory controller, storage device including the memory controller, and method of operating the memory controller and the storage device
KR102406449B1 (en) 2020-06-25 2022-06-08 에스케이하이닉스 주식회사 Storage device and operating method thereof
KR102435253B1 (en) 2020-06-30 2022-08-24 에스케이하이닉스 주식회사 Memory controller and operating method thereof
US11550658B1 (en) 2021-09-02 2023-01-10 Western Digital Technologies, Inc. Storage system and method for storing logical-to-physical address table entries in a codeword in volatile memory

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030177300A1 (en) * 2002-03-18 2003-09-18 Samsung Electro-Mechanics Co., Ltd. Data processing method in high-capacity flash EEPROM card system
US20040199738A1 (en) * 2001-04-20 2004-10-07 Jean-Paul Henriques Optimised storage addressing method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6804750B2 (en) * 2002-01-22 2004-10-12 Micron Technology, Inc. Technique for reducing memory latency during a memory request
JP2005025827A (en) 2003-06-30 2005-01-27 Toshiba Corp Semiconductor integrated circuit device and its error detecting and correcting method
US7301838B2 (en) 2004-12-13 2007-11-27 Innovative Silicon S.A. Sense amplifier circuitry and architecture to write data into and/or read from memory cells
US7447078B2 (en) 2005-04-01 2008-11-04 Sandisk Corporation Method for non-volatile memory with background data latch caching during read operations
WO2008139441A2 (en) * 2007-05-12 2008-11-20 Anobit Technologies Ltd. Memory device with internal signal processing unit
US8661218B1 (en) * 2007-10-18 2014-02-25 Datadirect Networks, Inc. Method for reducing latency in a solid-state memory system while maintaining data integrity
US8095763B2 (en) * 2007-10-18 2012-01-10 Datadirect Networks, Inc. Method for reducing latency in a raid memory system while maintaining data integrity
JP2010009646A (en) 2008-06-24 2010-01-14 Toshiba Memory Systems Co Ltd Semiconductor memory device
KR101780422B1 (en) * 2010-11-15 2017-09-22 삼성전자주식회사 Nonvolatile memory device, reading method thereof and memory system including the same
US9690953B2 (en) * 2013-03-14 2017-06-27 Apple Inc. Generating efficient reads for a system having non-volatile memory
US9645919B2 (en) * 2013-03-14 2017-05-09 Micron Technology, Inc. Memory systems and methods including training, data organizing, and/or shadowing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040199738A1 (en) * 2001-04-20 2004-10-07 Jean-Paul Henriques Optimised storage addressing method
US20030177300A1 (en) * 2002-03-18 2003-09-18 Samsung Electro-Mechanics Co., Ltd. Data processing method in high-capacity flash EEPROM card system

Also Published As

Publication number Publication date
TWI613675B (en) 2018-02-01
CN104995607A (en) 2015-10-21
CN104995607B (en) 2017-11-17
US20140281806A1 (en) 2014-09-18
TW201506953A (en) 2015-02-16
US9116824B2 (en) 2015-08-25
WO2014150516A2 (en) 2014-09-25

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