WO2016160032A1

WO2016160032A1 - Low power adc with pulsed bias

Info

Publication number: WO2016160032A1
Application number: PCT/US2015/024304
Authority: WO
Inventors: Branislav Petrovic; Gerrit Groenewold
Original assignee: Entropic Communications, Inc.
Priority date: 2015-04-03
Filing date: 2015-04-03
Publication date: 2016-10-06

Abstract

Systems and methods are provided for applying a pulsed bias for a short time to a receiver's ADC. The bias may be controlled by pulse amplitude, pulse width, or both. In one implementation, a receiver includes a pulsed bias control module for generating a pulsed bias signal; and an ADC including an amplifier coupled to an input analog signal and the pulsed bias signal. In one implementation, the receiver converts the input analog signal to a digital signal by: receiving the input analog signal at a first input of the amplifier; and sampling the input analog signal by generating the pulsed bias signal at a second input of the amplifier, and at approximately the same time as generating the pulsed bias signal applying a sampling pulse to a sampling switch coupled to an output of the amplifier.

Description

LOW POWER ADC WITH PULSED BIAS

Technical Field

The disclosed technology relates generally to communication systems, and more particularly, some embodiments relate to systems and methods for saving power in an analog-to- digital converter (ADC) by providing a dynamic bias control.

Description of the Related Art

Most analog communication signals have a high Peak to Average Power Ratio (PAPR). For instance, Radio Frequency (RF) OFDM signals have a ratio on the order of 25 or more. Traditional receivers such as low noise amplifiers (LNAs) and ADCs handle the peak power of a received signal by continuously applying a fixed and high bias as if the peak power is present all of the time.

For example, a unity gain buffer amplifier in a traditional ADC is biased continuously in order to track the input analog signal and ensure a sampling capacitor is charged (by closing a switch) at the time when the analog signal sampling is performed (by opening the switch). In this implementation, the bias must be high enough to ensure the capacitor is fully charged to the input analog signal value at the time of sampling. In the traditional ADC, the bias is applied all the time, regardless of the switch's position.

As another example, in traditional time-interleaved ADCs including N channels, the channels are charged sequentially using a fixed bias. The time when a channel's switch is closed charging the channel's sampling capacitor (i.e., channel's dwell time) is 1/N of the channel's cycle time. While the channel's capacitor is charging, the other channels are in the process of converting to digital, which may include intermittently toggling the other channels switches on and off (e.g., in a SAR architecture). Because of the limited isolation of the other channels, the toggling of the other channels may introduce crosstalk interference into the channel that is in the sampling phase, thereby introducing an error into the sampled value.

Brief Summary of Embodiments

According to various embodiments of the disclosed technology, a pulsed bias may be applied for a short time to a receiver ADC. In one embodiment, a transceiver for a communications device includes a receiver amplifier having an input coupled to a first output of a pulsed bias control module; the pulsed biased control module, where the pulsed bias control module has a second output coupled to a first input of an analog-to-digital converter (ADC); and the ADC, wherein the ADC has a second input coupled to the receiver amplifier. In this embodiment, the pulsed bias control module is configured to generate a pulsed bias. The bias may be controlled by pulse amplitude, pulse width, or both. In one embodiment, the receiver amplifier is a low-noise amplifier (LNA).

In one embodiment of the disclosed technology, the receiver amplifier includes a second input coupled to a closed loop calibration switch that when closed couples a transmitter section of the transceiver with the receiver amplifier. In one implementation of this embodiment, the receiver amplifier further includes a third input coupled to a transmit and receive switch of the transceiver. In various implementations, the transmit and receive switch may be open or set to a receive position when the closed loop calibration switch is closed.

In further implementations of this embodiment, the transceiver includes a calibration and digital correction digital signal processor (DSP), where an output of the ADC is coupled to an input of the DSP, and where the DSP is configured to generate a digital calibration signal used to calibrate the pulsed bias control module when the closed loop calibration switch is closed. In further implementations, the calibration and digital correction DSP has an output coupled to an input of a digital-to-analog converter (DAC) in the transmitter section of the transceiver, and the DAC receives the digital calibration signal as an input and outputs an analog calibration signal.

In another embodiment of the disclosed technology, a receiver includes a pulsed bias control module configured to generate a pulsed bias signal; and an ADC including an amplifier including a first input coupled to the received analog signal, and a second input coupled to an output of the pulsed bias control module. In this embodiment, the amplifier of the ADC is biased using the pulsed bias signal. In an implementation of this embodiment, the ADC includes a sampling switch coupled to an output of the amplifier, and the input analog signal is sampled by applying a sampling pulse to the sampling switch at a predetermined frequency. The pulsed bias signal may be turned on at approximately the same time as the sampling pulse, and turned off at approximately the same time as the sampling pulse.

In further embodiments, the ADC of the receiver is an interleaved ADC including N channels, each of the N channels including a sampling switch and sampling capacitor. In implementations of these embodiments the timescale of the sampling pulse may be substantially shorter than 1/N. In further implementations of these embodiments, the N channels may share a digital correction module.

In one embodiment, a receiver performs a method of converting an input analog signal to a digital signal by: receiving an input analog signal at a first input of an ADC amplifier; and sampling the input analog signal by: generating a pulsed bias signal at a second input of the amplifier; and at approximately the same time as generating the pulsed bias signal applying a sampling pulse to a sampling switch coupled to an output of the amplifier. In implementations of this embodiment, the receiver further performs the additional step of applying digital correction to the input analog signal, where the digital correction corrects any settling time errors or increased voltage across the amplifier caused by generating the pulsed bias signal at the second input of the amplifier.

Other features and aspects of the disclosed technology will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the features in accordance with embodiments of the disclosed technology. The summary is not intended to limit the scope of any inventions described herein, which are defined solely by the claims attached hereto.

Brief Description of the Drawings

The technology disclosed herein, in accordance with one or more various embodiments, is described in detail with reference to the following figures. The drawings are provided for purposes of illustration only and merely depict typical or example embodiments of the disclosed technology. These drawings are provided to facilitate the reader's understanding of the disclosed technology and shall not be considered limiting of the breadth, scope, or applicability thereof. It should be noted that for clarity and ease of illustration these drawings are not necessarily made to scale. Figure 1 is a diagram illustrating an example architecture for a communication module with which the technology disclosed herein may be implemented.

Figure 2 is a diagram illustrating an example receiver ADC with an envelope-controlled bias in accordance with one embodiment of the technology disclosed herein. Figure 3 is a diagram illustrating another example receiver ADC with an envelope- controlled bias in accordance with one embodiment of the technology disclosed herein.

Figure 4 is a diagram illustrating an example transceiver with an envelope-controlled bias in accordance with one embodiment of the technology disclosed herein. Figure 5 is a diagram illustrating an example interleaved ADC with an envelope- controlled bias in accordance with one embodiment of the technology disclosed herein.

Figure 6 is a diagram illustrating an example ADC with a pulse-controlled bias for a sample-and-hold circuit in accordance with one embodiment of the technology disclosed herein.

Figure 7A is a diagram illustrating a two-channel interleaved ADC with pulse-controlled bias in accordance with an embodiment of the disclosure.

Figure 7B illustrates an embodiment in which the stop-conversion pulses of an interleaved ADC are shared and the same as the bias pulses.

Figure 8 is a diagram illustrating an example transceiver with pulse-controlled bias in accordance with an embodiment of the technology disclosed herein. Figure 9 is a diagram illustrating an example ADC that combines a pulsed-controlled bias with an envelope-controlled bias in accordance with an embodiment of the technology disclosed herein.

FIG. 10 illustrates an example computing module that may be used in implementing various features of embodiments of the disclosed technology. The figures are not intended to be exhaustive or to limit the invention to the precise form disclosed. It should be understood that the invention can be practiced with modification and alteration, and that the disclosed technology be limited only by the claims and the equivalents thereof.

Detailed Description of the Embodiments As described above, conventional receivers are designed to handle the peak power of a received analog signal applying a continuous high bias as if the peak power is always present. However, in many communication signals the signal power is lower than the peak power for much, if not the majority, of the time. For example, in RF communications the signal power is the root mean square (RMS) power with brief excursions to higher and lower power levels. Accordingly, in various embodiments of the technology disclosed herein, systems and methods are provided for saving power in an analog-to-digital converter (ADC) for a receiver or transceiver by providing dynamic bias control.

In a first implementation of the technology disclosed herein, an envelope detection module determines the envelope or signal level of an analog input signal to be converted to a digital signal. Based on the determination of the signal envelope by the envelope detection module, a bias current, a bias voltage, or both are adjusted. In particular embodiments of the first implementation, the amount of applied bias may compensate for signal delay, signal noise, or some combination thereof. In this manner, significant power consumption savings may be achieved if the bias current, bias voltage, or both are high only when the signal level is high.

In a second implementation of the technology disclosed herein, a pulsed bias may be applied for a short time. The bias may be controlled by pulse amplitude, pulse width, or both. Because the pulsed bias permits rapid charging of a sampling capacitor in the ADC, significant power consumption savings may be achieved as substantially less time is spent charging one or more sampling capacitors in comparison to conventional constant biasing methods. Moreover, because the bias is not continuously applied, this reduces or altogether eliminates crosstalk interference issues in interleaved ADCs. In yet another implementation of the technology disclosed herein, a pulsed bias may be combined with an envelope-controlled bias.

Before describing the disclosed systems and methods in detail, it is useful to describe an example communication device with which they can be implemented. Figure 1 is a diagram illustrating an example communication device with which the technology disclosed herein may be implemented. After reading this description, one of ordinary skill in the art will appreciate that the technology disclosed herein can be used with any of a number of different devices or equipment having communication capabilities.

With reference now to Figure 1, in this example application, the example communication device 204 includes communication module 210 and one or more device functional modules 214. In this example, device functional modules 214 include an I/O interface module 308, functional modules 338, a control module 336, and a communication management module 334. Communication device 204 also includes a processor 306 (which can include multiple processors or processing units), and memory 310 (which can include memory units or modules of different types). Processor 306 and memory 310 can also be shared by communication module 210 (e.g., baseband module 341), or these components can include their own processors and memory. The various components of the communication device 204 are communicatively coupled via a bus 312 over which these modules may exchange and share information and other data.

I/O interface module 308, as provided in the illustrated example, can be configured to couple communication device 204 to other network nodes. These can include other network nodes or other equipment. In some embodiments, I/O interface module 308 comprises network interface circuitry, which in this example architecture includes a receiver module 318 and a transmitter module 320. These can, for example, include a communication receiver and a communication transmitter for wired or wireless communications across the network. Accordingly, communications via the I/O interface module 308 can, for example, be wired network communications, and the transmitter and receiver contained therein can include line drivers and receivers, as may be appropriate for the network communication interfaces. For example, I/O interface module 308 can be configured to interface with a network such as a MoCA network or an Ethernet network (although other network interfaces can be provided) or with a non-network physical connection. I/O interface module can also be configured to provide a wireless communication interface (e.g., Bluetooth, Zigbee, IEEE 802.11, and so on) including an antenna or antennas. Transmitter module 320 may be configured to transmit signals that can include data, beaconing and other MAC communications, and other information. These may be sent using a standard network protocol if desired. Receiver module 318 is configured to receive signals from other equipment. These signals can likewise include data and other communications from the other equipment, and can also be received in a standard network protocol if desired. Memory 310, can be made up of one or more modules of one or more different types of memory, and in the illustrated example is configured to store data and other information as well as operational instructions that may be used by the processor to operate communication device 204. The processor 306, which can be implemented as one or more cores, CPUs, DSPs, or other processor units, for example, is configured to execute instructions or routines and to use the data and information in memory 310 in conjunction with the instructions to control the operation of the communication device 204. For example, in the case of a set-top box program guides or other GUIs can be stored in memory 310 and used in the operation of communication device

204.

Other modules can also be provided with the communication device 204 depending on the equipment's intended function or purpose. A complete list of various additional components and modules would be too lengthy to include, however a few examples are illustrative. For example, a separate communication management module 334 can also be provided for the equipment to manage and control communications received from other entities, and to direct received communications as appropriate. Communication management module 334 can be configured to manage communication of various information sent to and received from other entities. Communication management module 334 can be configured to manage both wired and wireless communications.

A separate control module 336 can be included to control the operation of communication device 204. For example, control module 336 can be configured to implement the features and functionality of communication device 204. Functional modules 338 can also be included to provide other equipment functionality. For example, in the case of a set- top box, these modules (which may include various forms of hardware and software) can be provided to receive program content, decode received program content, convert the decoded content to an acceptable form for playback, and so on. As these examples illustrate, one of ordinary skill in the art will appreciate how other modules and components can be included with communication device 204 depending on the purpose or objectives of the equipment.

In this example, communication module 210 is configured as a transmit/receive module to transmit and receive analog signals via a wireless interface. Accordingly, while this example communication module includes a baseband module 341 to handle information in the digital domain, it also includes an analog-to-digital converter (ADC) 342 and a digital-to-analog converter (DAC) 343 to provide an analog interface to baseband module 341. A digital transceiver module can also be included to perform functions such as modulation and demodulation, upconversion and downconversion, filtering, and other functions for wireless communications. In this example, the transceiver module is illustrated as being in the same block as the baseband module. A power amplifier 345 may be included to amplify signals for transmission via antenna 349 across the wireless communication channel. Similarly, a low noise amplifier 346 can be included to amplify receive signals to a level useful for demodulation. A switch 348 can be included to allow a common antenna 349 to be shared between the transmit and receive paths. In other embodiments, the power amplifier 345 may be omitted and, for example, a Power DAC (PDAC) used to drive the antenna 349 directly via switch 348.

As noted above, prior receivers continuously apply a high bias to handle the peak power of a received analog signal. In embodiments of the systems and methods disclosed herein, a receiver's ADC can be provided with a dynamic bias control mechanism for adjusting the bias based on the varying power of the received signal. In various embodiments, illustrated by Figures 2-5, the bias is applied as a function of the received signal's envelope using an envelope detection and bias control module.

Although in some of these embodiments the envelope detection and bias control module is illustrated as an integrated component of the ADC, it is worth noting that in alternative embodiments the envelope detection and bias control module may be implemented as a standalone module or as part of other componentry. Furthermore, although illustrated as a single module, the envelope detection and bias control module of these embodiments may be implemented as a separate envelope detection module and a bias control module. For example, in one such implementation the envelope detection module may generate a control signal that drives the bias voltage or bias current output of the bias control module.

Figure 2 is a diagram illustrating example ADC 400 for a receiver with an envelope- controlled bias in accordance with one embodiment of the technology disclosed herein. As illustrated, ADC 400 comprises an envelope detection and bias control module 410 and a track and hold circuit 420 comprising a buffer amplifier 421, switch 422, capacitor 423, followed by quantization and digital conversion module 424. In various embodiments, ADC 400 may be implemented in a broadband receiver.

During operation, track and hold circuit 420 samples the entire band of the varying input analog signal. To sample the input analog signal, the switch 422 connects the output of buffer amplifier 421 to capacitor 423. The buffer amplifier 421 receives as inputs the input signal voltage and a bias determined by envelope detection and bias control module 410. Buffer amplifier 421 charges or discharges capacitor 423 such that the voltage across the capacitor is approximately equal to the input voltage from the analog signal. During a hold operation, switch 422 disconnects capacitor 423 from the output of buffer amplifier 421. It is worth noting that although the representative illustrations for the various switches in the drawings show the switches as mechanical switches or relays, one of ordinary skill in the art will understand how solid-state or semiconductor switches (e.g. using one or more transistors) can be used to implement these various switches.

In operation, envelope detection and bias control module 410 dynamically computes the signal envelope of the received analog signal. The envelope is derived from the entire analog signal's band, including the carrier signal and desired signal modulated on the carrier signal, and any other (undesired) signal contained inside the band. Based on the detected signal envelope, module 410 may dynamically adjust a bias voltage, bias current, or bias current and bias voltage supplied to buffer amplifier 421. Accordingly, the higher the envelope detected, the higher the applied bias, and the lower the envelope detected, the lower the applied bias. Such an implementation provides the benefit of reducing power dissipation while maintaining the performance of ADC 400 relative to conventional ADCs for receivers. In further embodiments, the dynamic bias may applied to other circuitry in the receiver such as a LNA.

In various embodiments, the bias is a linear or non-linear function of the detected envelope. In implementations of these embodiments, as the signal envelope decreases, the bias may be reduced at any rate above a minimum required bias. For example, consider the case where a minimum sufficient bias is 100mA and a maximum sufficient bias is 1A. In this example embodiment, power savings are maximized as the bias approaches the minimum value of 100mA.

On the other hand, as the bias approaches the minimum value, less accurate envelope detection methods suffice. This is because the power savings diminish (i.e. are non-linear) as the bias approaches the minimum value. For example, consider the case where a bias is applied within 10% of the ideal bias. In this example, where the ideal bias is 500 mA, the applied bias may be up to 550mA, or 50mA greater than the ideal bias. By contrast, where the ideal bias is 100 mA, the applied bias may be up to 110 mA, or 10mA greater than the ideal bias. But even if the applied bias was, for example, 15mA above the ideal bias, it would not significantly increase the power. Thus, the smaller the signal, the greater error (or margin above the ideal bias) that may be introduced into the bias calculation without significantly affecting the power efficiency of the bias control. Accordingly, in various embodiments the envelope detection and bias control module 410 may be configured to optimize tracking of the envelope for higher signal levels, while allowing for greater errors at lower signal levels. In implementations of these embodiments, any waveform that is monotonic with the envelope, and stays at or above ideal bias, may be used to determine the bias. In one embodiment, the envelope is detected using a rectifier. In this embodiment, module 410 rectifies the input signal, filters out the higher frequency terms of the signal, and passes the lower frequencies representing the envelope onto a biasing circuit. For example, consider a WiFi band of 5.17GHz to 5.835GHz. In this example, the bandwidth is 665MHz. Accordingly, the rectified envelope frequency will span 0 MHz (i.e., DC) to 665MHz. Higher frequencies centered around twice the RF frequency, i.e., approximately 11GHz, are filtered out using a lowpass filter.

Because the use of a filter introduces a delay into the rectified signal, the detected envelope will be delayed with respect to the analog signal received at buffer amplifier 421, thereby offsetting the dynamic bias (i.e., it is not based on the present envelope level). Accordingly, in implementations of the rectifier embodiment, the delay may be accounted for. The delay may be compensated by increasing the bias. For example, in one embodiment a margin is introduced into the signal envelope (and the dynamic bias) based on an estimate of the signal delay. In implementations of this embodiment, a margin for a particular delay time may be calculated by determining the maximum rate of change of the envelope voltage level as a function of time. For example, if the delay due to the bias filter is Ins, and the envelope voltage can increase by a maximum of lOOmV during this time, it may be determined that an additional bias current of, for example, 10mA is sufficient to keep the error at the acceptable level. In this example, a bias margin of 10mA may be added in the design of the circuit, thereby ensuring that errors due to the delay will be accounted for any envelope change that may occur during this delay time. In implementations, the delay introduced into the signal path may be determined during design of the ADC 400.

In an alternative embodiment, the analog signal received at buffer amplifier 421 may be delayed for approximately the same time as the time delay introduced by the filter. In implementations of the above embodiments, a filter with a flat delay such as a Gaussian filter may be utilized.

In another embodiment, the envelope is detected based on the I and Q channels of the received analog signal. In particular, because any bandlimited signal may be repres a sum of in phase (I) and quadrature components (Q), the envelope may be calculated as

Figure 3 is a diagram illustrating another example receiver ADC 500 with an envelope- controlled bias in accordance with one embodiment of the technology disclosed herein. Similar to ADC 400, ADC 500 comprises an envelope detection and bias control module 510, buffer amplifier 511, switch 512, capacitor 513, and quantization and digital conversion module 514. Additionally, ADC 500 comprises a digital correction module 515 that corrects errors that may occur in ADC 500 because of dynamic bias control. In one embodiment, the system may be trained to correct such errors. In this embodiment, a known calibration signal is applied across the entire ADC bandwidth and envelope detection range, the signal is digitized to compare digital values, and the determined digital values are compared with the expected digital values based on knowledge of the applied calibration signal's bandwidth and envelope. In this embodiment, for each sample of the calibration signal, digital correction module 515 may compute a correction value that equalizes the determined value with the expected value. Correction values may be determined and stored in memory (e.g., in a lookup table) for each possible input signal from 0 to the full scale of ADC 500. During operation (i.e., after training), when the actual signal is applied and processed, the correction values may be applied to each sample, thereby resulting in a corrected ADC output with correct digital words representing the converted analog value.

In an alternative embodiment, digital correction module 515 may correct for errors that occur in ADC 500 based on errors introduced at the maximum dynamic bias. Similar to the embodiment described above, an error correction value is determined for the maximum dynamic bias. Subsequently, when the actual signal is applied and processed, the maximum bias correction value may be applied to each sample.

In another embodiment, digital correction module 515 may correct errors based on an expected mean value of the sampled signal. For example, for a continuously varying analog signal centered about a zero mean value, the mean value of the sampled signal should also be zero. If it is not, the sampled signal may be offset by the difference between the expected zero mean and the actual mean value.

In a further embodiment, digital correction module 515 may correct for errors that occur in ADC 500 by modeling the distortion and error of buffer amplifier 511 during the design process. In this embodiment, the distortion and error may be modeled as a function of the signal level. Figure 4 is a diagram illustrating circuitry for an example transceiver 600 comprising a receiver section with an envelope-controlled bias in accordance with one embodiment of the technology disclosed herein. Transceiver 600 includes a transmit section comprising digital-to- analog converter (DAC) 601, power amplifier (PA) 602, and a receiver section comprising receive amplifier 621 such as a LNA, ADC 622, and envelope detection and bias control module 623. Also illustrated are antenna 612, band-pass filter (BPF) 611, a transmit/receive switch 613, a switch 614 to switch to closed loop calibration, a loop resistor 605, and calibration and digital correction digital signal processor (DSP) 630.

As illustrated in this embodiment, transceiver 600 includes a calibration loop (closed switch 614) for measuring and storing digital correction values for errors that occur in the receiver path due to dynamic bias correction to ADC 622, receive amplifier 621, or both. During calibration, a calibration signal may be generated in DSP 630, converted to an analog signal by DAC 601, amplified by PA 602, and looped back to receiver amplifier 621. Envelope detection and bias control module 623 detects the envelope of the looped analog signal and applies a dynamic bias to the ADC 622, amplifier 621, or both. ADC 622 then feeds back a digitized signal to DSP 630. Subsequently, the signal of DAC 601 may be stepped through all levels of ADC 622 to calibrate each level. The signal that is fed back is compared to the original signal by DSP 630. As a result of the comparison, differences between the original digital signal and the feedback digital signal can be determined, stored (e.g., in memory of DSP 630), and used as a basis for error correction of the digital signal output by ADC 622.

In an alternative embodiment, the bias is adjusted by adjusting the gain or the coupling of a bias control signal to minimize the total error summed over all ADC levels. This adjustment may include several iterations using different bias control signal parameters until a minimum error is achieved. The residual errors are then digitally corrected to within acceptable levels, as described above. In another embodiment, the error sum of only higher MSB bits is minimized. In this embodiment, the calibration is followed and completed by digital correction.

In various embodiments, calibration may be performed upon power up, upon tuning, periodically in a maintenance loop (e.g., a loop closed when transceiver 600 is not transmitting or receiving traffic), or any combination thereof. In one embodiment, illustrated in Figure 4, receive/transmit switch 613 may be placed in a neutral or open position so as not to radiate energy in the calibration mode or receive off-air signals that may interfere with calibration. Alternatively, in another embodiment calibration may be performed with receive/transmit switch 613 in a receive position. In one embodiment, loop resistor 605 is designed for higher impedance than filter 611 and antenna 612. In this embodiment, when switch 613 is in the receive position and switch 614 is in calibration (closed) position, amplifier 621 sees substantially the same impedance as during normal operation (set by filter 611/antenna 612), thereby emulating approximately normal operating conditions and facilitating the accuracy of the calibration.

In various embodiments, components such as DAC 601 and PA 602 can be those components normally used for the transmit chain of the transceiver. Accordingly, real estate and power can be conserved. However, in such embodiments, priority may be given to transmit operations over calibration of the bias control of the receiver section. Accordingly, in some embodiments, the system can be implemented to conduct a calibration run prior to actual operation. In such embodiments, calibration tables can be created based on corrected values determined, if any, during the calibration run. Then during actual operation, the stored tables can be applied by DSP 630 in real time. In other embodiments, a dedicated feedback path can be provided for error detection and correction.

In alternative embodiments, the described calibration method may be applied to receivers only. In such embodiments, a closed loop calibration may be applied by looping a DAC with the receiver circuit. The DAC may generate test digital signals that are looped back through the receiver path.

In additional embodiments, the described calibration method may implemented in a transceiver comprising multiple transmit and receive antennas (e.g., a MIMO architecture) and in wired mediums such as coaxial cable networks (e.g., MoCA networks).

Figure 5 is a diagram illustrating an example N-channel interleaved ADC 700 with an envelope-controlled bias for a receiver in accordance with one embodiment of the technology disclosed herein. As illustrated, interleaved ADC 700 comprises envelope detection and bias control module 702, transistors 706A and 706B, and N sampling channels including switches 708A-N, and sampling capacitors 710A-710N. Although ADC 700 is illustrated as a single- ended circuit with single supply rail Vdd, in alternative embodiments ADC 700 may be implemented as a differential circuit. In various embodiments, transistors 706A-B may be implemented as the illustrated N- type field effect transistors (FETs) or as P-type FETs. During operation, as the bias control signal voltage B(t) varies at the gate of transistor 706B, the Idd current may increase approximately as a square of the gate voltage. Accordingly, a higher bias signal B(t) reduces the source resistance of transistor 706A, thereby speeding up charging or discharging of sampling capacitors 710A-710N depending on whether the new sampled value is higher or lower than the capacitor voltage. Following this operation, the target sampling level (e.g., less than one LSB of the signal level) may be reached within the time allocated for the charging of each channel. Conversely, a lower bias signal B(t) increases the source resistance of transistor 706A, thereby slowing down the charging or discharging of capacitors 710A-710N, but still permitting enough time to charge to the lower sampled value.

Accordingly, modulation of the bias current Idd with the envelope of the received signal may result in substantially lower power consumption, as the average Idd current is substantially lower than the peak Idd for signals with high peak-to average power ratio, which is generally true of most communication signals.

In one embodiment of envelope detection and bias control module 702, the bias control signal B(t) is proportional to the envelope of the input analog signal. In another embodiment, bias control signal B(t) is proportional to the square of the envelope signal. In yet another embodiment, bias control signal B(t) is proportional to the square root of the envelope signal.

With reference now to Figures 6-9, systems and methods are illustrated for applying a pulse-modulated bias in an ADC for a receiver. In various embodiments, further described below, the pulsed bias may be controlled by pulse amplitude, pulse width, or both. Because the pulsed bias permits rapid charging of a sampling capacitor in the ADC, substantially less time is spent charging one or more sampling capacitors in comparison to conventional constant biasing methods.

Figure 6 is a diagram illustrating an example ADC 800 with a pulse-controlled bias for a sample-and-hold circuit in accordance with one embodiment of the technology disclosed herein. As illustrated, ADC 800 comprises a pulsed bias control module 804, and a sample and hold circuit comprising buffer amplifier 802, switch 806, sampling capacitor 808, and pulse sampling module 812, followed by quantization and digital conversion module 810 and digital correction module 814. During operation of the sample and hold circuit, an input analog signal is sampled by applying a sampling pulse to switch 806 at a predetermined sampling frequency (e.g., higher than the Nyquist frequency). Switch 806 is closed for the duration of the sampling pulse.

In various embodiments, pulsed bias control module 804 generates a pulsed bias at the same time or slightly before pulsed sampling module 812 generates a sampling pulse. The pulsed bias is turned off at the same time (or slightly after) sampling switch 806 opens. Because the sampling time is much shorter than in conventional biasing solutions, the bias is turned off most of the time, thereby saving power. During operation of the pulsed bias, the bias current is several times greater than the continuous bias generated by conventional biasing approaches. For example, consider a conventional biasing technique that generates a continuous bias current of 200mA. In this particular example, the pulsed bias of the present disclosure may be as high as 1A or 2A (i.e., a factor of 5 to 10) during the brief period of time that the pulsed bias is ON.

In embodiments, the amplitude of the pulse is the full Vdd or a voltage scaled-down from Vdd, independent of the received signal. In implementations of these embodiments, the pulse width may be determined by design. Alternatively, in other embodiments, the pulse width may be determined by a calibration method that minimizes the error introduced by the pulse bias to an acceptable level. One such method is described below with reference to Figure 8.

In various embodiments, a bypass capacitor (not shown in Figure 6) at a supply rail near buffer amplifier 802 may supply the high current, short duration bias. The source impedance of buffer amplifier 802 is substantially lower than in conventional implementations because of the high bias current during the pulsed bias, thereby improving the charging time of capacitor 808 such that it can fully charge with a shorter sampling pulse duration.

In embodiments, digital correction module 814 may apply digital correction to correct any settling time errors, increased voltage across buffer amplifier 802, or both that may occur because of the pulsed, high current bias. In further embodiments, the pulsed bias can be applied to other componentry of the receiver such as a receiver amplifier (e.g., a LNA), separately or in conjunction with the ADC pulsed bias.

In various embodiments, a pulse-controlled bias may be implemented in an interleaved ADC comprising any number of channels N (e.g., 2, 8, 16, etc.). In implementations of such embodiments the time scale of a sampling pulse may be substantially shorter than 1/N (e.g., by a factor of 5 or more). Further, in implementations of such embodiments digital conversion may be halted while a channel's sampling capacitor is being charged, thereby eliminating error- inducing interference (e.g., crosstalk) between the channels.

Figure 7A is a diagram illustrating one such embodiment of a two-channel interleaved ADC 900 with pulse-controlled bias. ADC 900 comprises a buffer amplifier 902, pulsed bias control module 904, and two channels, each channel comprising a sampling switch 906A-906B, a capacitor 908A-908B, a quantization and digital conversion module 910A-910B, and a digital correction module 912A-912B. Although illustrated as a two-channel ADC, one having ordinary skill art would understand that ADC 900 could be generalized to any number of channels N.

In one embodiment, illustrated by Figures 7A-7B, the same stop-conversion pulses may be applied to all channels, including the N-l channels that are in the conversion phase and the N^th channel that is in the sampling phase. In an implementation of this embodiment, illustrated by Figure 7B, the stop-conversion pulses may be the same as the bias pulses and may be shared from the same driver module. In another embodiment, each of the N channels may share a single digital correction module.

In a further embodiment, the pulsed bias is not completely turned off in between samples. Rather, the pulse biased is reduced to a lower level, for example to one tenth of the peak, to reduce transients, to increase the isolation between switches of different channels when in the off-position, or both.

Figure 8 is a diagram illustrating an example transceiver 1000 with pulse-controlled bias in accordance with another embodiment of the technology disclosed herein. Transceiver 1000 includes a transmit section comprising digital-to-analog converter (DAC) 1001, power amplifier (PA) 1002, and a receiver section comprising receive amplifier 1021 such as a LNA, ADC 1022, and pulsed bias control module 1023. Also illustrated are antenna 1012, band-pass filter (BPF) 1011, a transmit/receive switch 1013, a switch 1014 to switch to closed loop calibration, a loop resistor 1005, and calibration and digital correction digital signal processor (DSP) 1030.

As illustrated in this embodiment, transceiver 1000 includes a calibration loop (closed switch 1014) for measuring and storing digital correction values for errors that occur in the receiver path due to pulsed biased applied to ADC 1022, receive amplifier 1021, or both. During calibration, a calibration signal may be generated in DSP 1030, converted to an analog signal by

DAC 1001, amplified by PA 1002, and looped back to receiver amplifier 1021. Subsequently, the signal of DAC 1001 may be stepped through all levels of ADC 1022 to calibrate each level.

In this implementation, ADC 1022 feeds back a digitized signal to DSP 1030. The signal that is fed back is compared to the original signal by DSP 1030. As a result of the comparison, differences between the original digital signal and the feedback digital signal can be determined, stored (e.g., in memory of DSP 1030), and used as a basis for error correction of the digital signal output by ADC 1022.

In an alternative embodiment, the bias is adjusted (by adjusting the pulse amplitude, the pulse width or both) to minimize the total error summed over all ADC levels. This adjustment may include several iterations using different pulse parameters (level/width) until a minimum error is achieved. The residual errors are then digitally corrected to within acceptable levels, in the same way as described above. In another embodiment, the error sum of only higher MSB bits is minimized. In this embodiment, the calibration is followed and completed by digital correction.

In various embodiments, calibration may be performed upon power up, upon tuning, periodically in a maintenance loop, or some combination thereof as described above with reference to Figure 4. Similarly, as described above, a calibration run may be conducted prior to actual operation.

In embodiments, a dedicated feedback path can be provided for error detection and correction. In additional embodiments, the described calibration method may be applied to receivers only. In such embodiments, a closed loop calibration may be applied by looping a DAC with the receiver circuit. The DAC may generate test digital signals that are looped back through the receiver path. In further embodiments, the described calibration method may implemented in a transceiver comprising multiple transmit and receive antennas (e.g., a MEVIO architecture) and in wired mediums such as coaxial cable networks (e.g., MoCA networks). In yet further embodiments, an envelope detection and bias control module 623, as described in Figure 4, may be incorporated into transceiver 1000 to provide further reduction in power consumption. For example, in one implementation a pulsed bias signal amplitude or width may be adjusted based on a detected signal envelope.

Figure 9 is a diagram illustrating an example ADC 1100 that combines a pulsed- controlled bias with an envelope-controlled bias. ADC 1100 includes envelope detection and bias control module 1101, transistors 1102-1104, pulse bias control module 1105, sampling switches 1106A-1106N, and sampling capacitors 1107A-1107N.

In operation, transistor 1104 may be controlled by pulses generated by pulse bias control module 1105 at its gate. The generated pulses are synchronized with the sample pulses that operate sampling switches 1106A-1106N. In this embodiment, the voltage of the generated pulses is Vdd, the voltage provided at the supply rail 1108, which causes saturation of transistor 1104. When the pulse is ON, the current flowing through transistor 1104 is added of transistor 1102 flowing through transistor 1003. In such embodiments, the current through transistor 1104 is a function of the size of transistor 1104. Alternatively, when the pulse is OFF, the bias current falls back to the one provided by transistor 1103 based on bias control signal B(t).

In various embodiments of ADC 1100, the envelope controlled bias and pulsed bias may be combined by multiplication, summation or other combination (not shown in Figure 9). For example, the pulsed biased may be used to adjust the amplitude of the enveloped controlled biased. Conversely, the enveloped controlled bias may adjust the duration, amplitude, or both of the pulsed biased. Alternatively, the enveloped controlled bias and pulsed bias may follow different signal paths.

In one embodiment, the gate of transistor 1103 may be disconnected from envelope detection and bias control module 1101 and connected to a fixed voltage, thereby providing a constant bias through transistor 1103. In this embodiment, the pulsed bias may be added to this fixed bias when the pulse is ON.

In another embodiment, transistor 1103 may be removed, thereby limiting bias control to transistor 1104. In another embodiment, the voltage of the pulsed bias may be proportional to the detected envelope signal level B(t). In one example implementation of this embodiment, a low-dropout (LDO) may track the envelope signal level B(t) and control both the voltage of the pulse as well as the bias applied along transistor 1103.

As used herein, the term module might describe a given unit of functionality that can be performed in accordance with one or more embodiments of the technology disclosed herein. As used herein, a module might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FPGAs, logical components, software routines or other mechanisms might be implemented to make up a module. In implementation, the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules. In other words, as would be apparent to one of ordinary skill in the art after reading this description, the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Even though various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality can be shared among one or more common software and hardware elements, and such description shall not require or imply that separate hardware or software components are used to implement such features or functionality.

Where components or modules of the technology are implemented in whole or in part using software, in one embodiment, these software elements can be implemented to operate with a computing or processing module capable of carrying out the functionality described with respect thereto. One such example computing module is shown in Figure 10. Various embodiments are described in terms of this example-computing module 1200. After reading this description, it will become apparent to a person skilled in the relevant art how to implement the technology using other computing modules or architectures.

Referring now to Figure 10, computing module 1200 may represent, for example, computing or processing capabilities found within desktop, laptop and notebook computers; hand-held computing devices (PDA's, smart phones, cell phones, palmtops, etc.); mainframes, supercomputers, workstations or servers; or any other type of special-purpose or general-purpose computing devices as may be desirable or appropriate for a given application or environment. Computing module 1200 might also represent computing capabilities embedded within or otherwise available to a given device. For example, a computing module might be found in other electronic devices such as, for example, digital cameras, navigation systems, cellular telephones, portable computing devices, modems, routers, WAPs, terminals and other electronic devices that might include some form of processing capability.

Computing module 1200 might include, for example, one or more processors, controllers, control modules, or other processing devices, such as a processor 1204. Processor 1204 might be implemented using a general-purpose or special-purpose processing engine such as, for example, a microprocessor, controller, or other control logic. In the illustrated example, processor 1204 is connected to a bus 1202, although any communication medium can be used to facilitate interaction with other components of computing module 1200 or to communicate externally.

Computing module 1200 might also include one or more memory modules, simply referred to herein as main memory 1208. For example, preferably random access memory (RAM) or other dynamic memory, might be used for storing information and instructions to be executed by processor 1204. Main memory 1208 might also be used for storing temporary variables or other intermediate information during execution of instructions to be executed by processor 1204. Computing module 1200 might likewise include a read only memory ("ROM") or other static storage device coupled to bus 1202 for storing static information and instructions for processor 1204.

The computing module 1200 might also include one or more various forms of information storage mechanism 1210, which might include, for example, a media drive 1212 and a storage unit interface 1220. The media drive 1212 might include a drive or other mechanism to support fixed or removable storage media 1214. For example, a hard disk drive, a floppy disk drive, a magnetic tape drive, an optical disk drive, a CD or DVD drive (R or RW), or other removable or fixed media drive might be provided. Accordingly, storage media 1214 might include, for example, a hard disk, a floppy disk, magnetic tape, cartridge, optical disk, a CD or DVD, or other fixed or removable medium that is read by, written to or accessed by media drive 1212. As these examples illustrate, the storage media 1214 can include a computer usable storage medium having stored therein computer software or data.

In alternative embodiments, information storage mechanism 1210 might include other similar instrumentalities for allowing computer programs or other instructions or data to be loaded into computing module 1200. Such instrumentalities might include, for example, a fixed or removable storage unit 1222 and an interface 1220. Examples of such storage units 1222 and interfaces 1220 can include a program cartridge and cartridge interface, a removable memory (for example, a flash memory or other removable memory module) and memory slot, a PCMCIA slot and card, and other fixed or removable storage units 1222 and interfaces 1220 that allow software and data to be transferred from the storage unit 1222 to computing module 1200.

Computing module 1200 might also include a communications interface 1224. Communications interface 1224 might be used to allow software and data to be transferred between computing module 1200 and external devices. Examples of communications interface 1224 might include a modem or softmodem, a network interface (such as an Ethernet, network interface card, WiMedia, IEEE 802.XX or other interface), a communications port (such as for example, a USB port, IR port, RS232 port Bluetooth® interface, or other port), or other communications interface. Software and data transferred via communications interface 1224 might typically be carried on signals, which can be electronic, electromagnetic (which includes optical) or other signals capable of being exchanged by a given communications interface 1224. These signals might be provided to communications interface 1224 via a channel 1228. This channel 1228 might carry signals and might be implemented using a wired or wireless communication medium. Some examples of a channel might include a phone line, a cellular link, an RF link, an optical link, a network interface, a local or wide area network, and other wired or wireless communications channels.

In this document, the terms "computer program medium" and "computer usable medium" are used to generally refer to media such as, for example, main memory 1208, storage unit 1220, storage media 1214, and channel 1228. These and other various forms of computer program media or computer usable media may be involved in carrying one or more sequences of one or more instructions to a processing device for execution. Such instructions embodied on the medium, are generally referred to as "computer program code" or a "computer program product" (which may be grouped in the form of computer programs or other groupings). When executed, such instructions might enable the computing module 1200 to perform features or functions of the disclosed technology as discussed herein.

While various embodiments of the disclosed technology have been described above, it should be understood that they have been presented by way of example only, and not of limitation. Likewise, the various diagrams may depict an example architectural or other configuration for the disclosed technology, which is done to aid in understanding the features and functionality that can be included in the disclosed technology. The disclosed technology is not restricted to the illustrated example architectures or configurations, but the desired features can be implemented using a variety of alternative architectures and configurations. Indeed, it will be apparent to one of skill in the art how alternative functional, logical or physical partitioning and configurations can be implemented to implement the desired features of the technology disclosed herein. Also, a multitude of different constituent module names other than those depicted herein can be applied to the various partitions. Additionally, with regard to flow diagrams, operational descriptions and method claims, the order in which the steps are presented herein shall not mandate that various embodiments be implemented to perform the recited functionality in the same order unless the context dictates otherwise.

Although the disclosed technology is described above in terms of various exemplary embodiments and implementations, it should be understood that the various features, aspects and functionality described in one or more of the individual embodiments are not limited in their applicability to the particular embodiment with which they are described, but instead can be applied, alone or in various combinations, to one or more of the other embodiments of the disclosed technology, whether or not such embodiments are described and whether or not such features are presented as being a part of a described embodiment. Thus, the breadth and scope of the technology disclosed herein should not be limited by any of the above-described exemplary embodiments.

Terms and phrases used in this document, and variations thereof, unless otherwise expressly stated, should be construed as open ended as opposed to limiting. As examples of the foregoing: the term "including" should be read as meaning "including, without limitation" or the like; the term "example" is used to provide exemplary instances of the item in discussion, not an exhaustive or limiting list thereof; the terms "a" or "an" should be read as meaning "at least one," "one or more" or the like; and adjectives such as "conventional," "traditional," "normal," "standard," "known" and terms of similar meaning should not be construed as limiting the item described to a given time period or to an item available as of a given time, but instead should be read to encompass conventional, traditional, normal, or standard technologies that may be available or known now or at any time in the future. Likewise, where this document refers to technologies that would be apparent or known to one of ordinary skill in the art, such technologies encompass those apparent or known to the skilled artisan now or at any time in the future. The presence of broadening words and phrases such as "one or more," "at least," "but not limited to" or other like phrases in some instances shall not be read to mean that the narrower case is intended or required in instances where such broadening phrases may be absent. The use of the term "module" does not imply that the components or functionality described or claimed as part of the module are all configured in a common package. Indeed, any or all of the various components of a module, whether control logic or other components, can be combined in a single package or separately maintained and can further be distributed in multiple groupings or packages or across multiple locations. Additionally, the various embodiments set forth herein are described in terms of exemplary block diagrams, flow charts and other illustrations. As will become apparent to one of ordinary skill in the art after reading this document, the illustrated embodiments and their various alternatives can be implemented without confinement to the illustrated examples. For example, block diagrams and their accompanying description should not be construed as mandating a particular architecture or configuration.

Claims

Claims What is claimed is:

1. A transceiver for a communications device, comprising: a receiver amplifier having an input coupled to a first output of a pulsed bias control module; the pulsed bias control module, wherein the pulsed bias control module has a second output coupled to a first input of an analog-to-digital converter (ADC), and wherein the pulsed bias control module is configured to generate a pulsed bias; and the ADC, wherein the ADC has a second input coupled to the receiver amplifier.

2. The transceiver of claim 1, wherein the receiver amplifier comprises a second input coupled to a closed loop calibration switch that when closed couples a transmitter section of the transceiver with the receiver amplifier.

3. The transceiver of claim 2, wherein the receiver amplifier further comprises a third input coupled to a transmit and receive switch of the transceiver.

4. The transceiver of claim 2, further comprising a calibration and digital correction digital signal processor (DSP), wherein an output of the ADC is coupled to an input of the DSP, and wherein the DSP is configured to generate a digital calibration signal used to calibrate the pulsed bias control module when the closed loop calibration switch is closed.

5. The transceiver of claim 4, wherein the calibration and digital correction DSP has an output coupled to an input of a digital-to-analog converter (DAC) in the transmitter section of the transceiver, and wherein the DAC receives the digital calibration signal as an input and outputs an analog calibration signal.

6. The transceiver of claim 3, wherein the transmit and receive switch is open when the closed loop calibration switch is closed.

7. The transceiver of claim 1, wherein the receiver amplifier is a low-noise amplifier (LNA).

8. A receiver comprising: a pulsed bias control module configured to generate a pulsed bias signal; and an analog-to-digital converter (ADC), comprising an amplifier comprising a first input coupled to the received analog signal, and a second input coupled to an output of the pulsed bias control module, wherein the amplifier is biased based on the pulsed bias signal.

9. The receiver of claim 8, further comprising a sampling switch coupled to an output of the amplifier, wherein an input analog signal is sampled by applying a sampling pulse to the sampling switch at a predetermined frequency.

10. The receiver of claim 9, wherein the pulsed bias signal is turned on at approximately the same time as the sampling pulse, and wherein the pulsed bias signal is turned off at approximately the same time as the sampling pulse.

11. The receiver of claim 8, further comprising a digital correction module configured to apply digital correction to correct any settling time errors or increased voltage across the amplifier that may occur because of the pulsed bias signal.

12. The receiver of claim 8, further comprising a LNA, and wherein the pulsed bias signal is applied to an input of the LNA.

13. The receiver of claim 9, wherein the ADC is an interleaved ADC comprising a plurality of N channels, each of the N channels comprising a sampling switch and sampling capacitor.

14. The receiver of claim 13, wherein the timescale of the sampling pulse is substantially shorter than 1/N.

15. The receiver of claim 13, wherein digital conversion is paused while a sampling channel's capacitor is being charged.

16. The receiver of claim 13, wherein the plurality of N channels share a digital correction module.

17. A method of converting an input analog signal to a digital signal in a receiver, comprising: receiving an input analog signal at a first input of an amplifier; and sampling the input analog signal by: generating a pulsed bias signal at a second input of the amplifier; and at approximately the same time as generating the pulsed bias signal applying a sampling pulse to a sampling switch coupled to an output of the amplifier.

18. The method of claim 17, wherein the pulsed bias signal is turned on at approximately the same time as the sampling pulse, and wherein the pulsed bias signal is turned off at approximately the same time as the sampling pulse.

19. The method of claim 18, further comprising applying digital correction to the input analog signal, wherein the digital correction corrects any settling time errors or increased voltage across the amplifier caused by generating the pulsed bias signal at the second input of the amplifier.

20. The method of claim 17, further comprising applying a plurality of sampling pulses to a plurality of sampling switches coupled in parallel.