An array-word-organized memory system comprising a plurality of columns and rows of memory chips, an address bus routed through all of the memory chips, a plurality of selectable CAS lines wherein one of the CAS lines is routed through each one of said plurality of columns of memory chips and a plurality...http://www.google.de/patents/US4773044?utm_source=gb-gplus-sharePatent US4773044 - Array-word-organized display memory and address generator with time-multiplexed address bus
