An integrated circuit chip has a multi-layer input/output pad interconnection structure which allows input/output buffers to be flexibly coupled to input/output pads depending on the chip's applications. To obtain the multi-layer pad interconnection structure, a first interconnection layer is formed...http://www.google.de/patents/US6159774?utm_source=gb-gplus-sharePatent US6159774 - Multi-layer interconnection layout between a chip core and peripheral devices
