A method of synthesizing a clock tree for reducing peak power in an integrated circuit design includes partitioning a circuit design into a set of memory cells and a set of non-memory cells, partitioning the set of memory cells into segments, constructing a first clock tree having a first root vertex...http://www.google.de/patents/US6941533?utm_source=gb-gplus-sharePatent US6941533 - Clock tree synthesis with skew for memory devices
