A folded bitline dynamic RAM circuit with reduced shared supply voltages comprised of circuitry for applying full logic high and low supply voltages to respective bitlines during successive active cycles of the RAM circuit, and circuitry for applying reduced supply voltages to the bitlines during successive...http://www.google.de/patents/US4980862?utm_source=gb-gplus-sharePatent US4980862 - Folded bitline dynamic ram with reduced shared supply voltages
