An integrated circuit fabrication process is provided in which copper is used as the contact plug material for a via. The via is a hole etched through an interlevel dielectric which is disposed upon a semiconductor topography, e.g., a silicon-based substrate having junctions therein. An inert...http://www.google.de/patents/US5770517?utm_source=gb-gplus-sharePatent US5770517 - Semiconductor fabrication employing copper plug formation within a contact area 
