It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in an E/R type 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors and two load resistor elements, each of the MOS transistor constituting the memory cell...http://www.google.de/patents/US8154086?utm_source=gb-gplus-sharePatent US8154086 - Semiconductor surround gate SRAM storage device
