An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by...http://www.google.de/patents/US6801465?utm_source=gb-gplus-sharePatent US6801465 - Apparatus and method for a memory storage cell leakage cancellation scheme
