An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write operation...http://www.google.de/patents/US6240040?utm_source=gb-gplus-sharePatent US6240040 - Multiple bank simultaneous operation for a flash memory
