A method for describing a user programmable logic function generator in a Hardware Description Language (HDL), e.g., Verilog is disclosed. The logic function generator includes a multiplexer having a plurality of select inputs and a plurality of programmable data inputs. The logic function generator...http://www.google.de/patents/US6594816?utm_source=gb-gplus-sharePatent US6594816 - Method and an apparatus for synthesizing a programmable logic circuit
