There is disclosed a data processor having a clustered architecture that comprises a plurality of clusters, an instruction cache and a power-down controller. Each of the clusters comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing...http://www.google.de/patents/US6772355?utm_source=gb-gplus-sharePatent US6772355 - System and method for reducing power consumption in a data processor having a clustered architecture
