A memory cell has a vertical MOS transistor which contains a first electrically insulated gate electrode and a second gate electrode. The second gate electrode is partially disposed in a trench whose sidewall is adjoined by the MOS transistor. The first gate electrode is disposed outside the trench and...http://www.google.de/patents/US6316315?utm_source=gb-gplus-sharePatent US6316315 - Method for fabricating a memory cell having a MOS transistor
