In an integrated logic curcuit, a plurality of clock skew adjustors generate clocks having coincident phases in reaponse to frequency information and phase information fed from a clock source. These clock source and clock adjustors are arranged so that their individual signal delays may be substantially...http://www.google.de/patents/US5122679?utm_source=gb-gplus-sharePatent US5122679 - Integrated logic circuit with clock skew adjusters
