A register interference state where a register which is updated by a preceding instruction is used by a succeeding instruction, for example, for the generation of an operand address, is detected. When a register interference state is detected, the execution of a succeedingly fetched instruction is started...http://www.google.de/patents/US6421771?utm_source=gb-gplus-sharePatent US6421771 - Processor performing parallel operations subject to operand register interference using operand history storage
