A series-parallel-series memory or other parallel-to-series CCD has charge-signals interlaced in alternate parallel channels 1a and 1b, and de-interlacing electrodes (19, 20, 21, 22) at the parallel-to-series transition. In order to avoid delay effects as a result of comb-shaped electrode configurations...http://www.google.de/patents/US4669100?utm_source=gb-gplus-sharePatent US4669100 - Charge-coupled device having a buffer electrode
