In a video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit....http://www.google.de/patents/US5210639?utm_source=gb-gplus-sharePatent US5210639 - Dual-port memory with inhibited random access during transfer cycles with serial access
