A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and...http://www.google.de/patents/US6403485?utm_source=gb-gplus-sharePatent US6403485 - Method to form a low parasitic capacitance pseudo-SOI CMOS device
