A write-back cache control system having a pending write-back cache controller in a multiprocessor cache memory structure. The processor subsystems in the multiprocessor system are coupled together using a high-speed synchronous packet switching bus called a memory bus. Each processor subsystem has an...http://www.google.de/patents/US5434993?utm_source=gb-gplus-sharePatent US5434993 - Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories
