A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those...http://www.google.de/patents/US6356972?utm_source=gb-gplus-sharePatent US6356972 - System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom
