A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each formed via one of either selective growth, epitaxial...http://www.google.de/patents/US5414288?utm_source=gb-gplus-sharePatent US5414288 - Vertical transistor having an underlying gate electrode contact
