A transistor and transistor fabrication method are presented where a sequence of layers are formed and either entirely or partially removed upon sidewall surfaces of a gate conductor. The formation and removal of layers produces a lateral surface to which various implants can be aligned. Those implants,...http://www.google.de/patents/US6083846?utm_source=gb-gplus-sharePatent US6083846 - Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon
