A cache system which, when a cache is a bus master, puts a CPU in a standby state and makes effective a signal common to the CPU and cache and a signal decided only by the cache, or when the CPU is the bus master, makes effective the signal common to the CPU and cache and the signal decided only by the...http://www.google.de/patents/US5185879?utm_source=gb-gplus-sharePatent US5185879 - Cache system and control method therefor
