A semiconductor integrated circuit device with the SOI structure is provided, which decreases the chip area of wiring lines interconnecting p- and n-channel IGFETs, raising their integration level. This device is comprised of a semiconductor layer formed on an insulating substrate. The semiconductor...http://www.google.de/patents/US6037617?utm_source=gb-gplus-sharePatent US6037617 - SOI IGFETs having raised integration level
