A data processing system which employs a cache memory feature and a method for lowering the cache miss ratio for called operands in the data processing system are disclosed. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement...http://www.google.de/patents/US5701426?utm_source=gb-gplus-sharePatent US5701426 - Data processing system and method using cache miss address prediction and forced LRU status in a cache memory to improve cache hit ratio 
