A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The drain region is...http://www.google.de/patents/US6952033?utm_source=gb-gplus-sharePatent US6952033 - Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line
