A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide...http://www.google.de/patents/US7577027?utm_source=gb-gplus-sharePatent US7577027 - Multi-state memory cell with asymmetric charge trapping
