A clock generating circuit for compensating for a delay difference using a closed loop analog synchronous mirror delay structure is provided. The clock generating circuit divides a delay clock signal and a reference clock signal to generate first and second divided signals, and synchronizes an internal...http://www.google.de/patents/US6437613?utm_source=gb-gplus-sharePatent US6437613 - Clock generating circuit for compensation of delay difference using closed loop analog synchronous mirror delay structure
