The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement...http://www.google.de/patents/US6909306?utm_source=gb-gplus-sharePatent US6909306 - Programmable multi-standard I/O architecture for FPGAS
