A memory circuit has a plurality of bit line pairs and intersecting word lines with a memory cell located at each such intersection. A column address selects the bit line which is to be accessed and a row address selects the word line which is enabled. Memory cells along an enabled word line cause the...http://www.google.de/patents/US4658381?utm_source=gb-gplus-sharePatent US4658381 - Bit line precharge on a column address change
