A combined adder/decoder calculates a field within an effective address necessary to access a translation array. Rather than adding the full lengths of the previous fetch address and offset, only the bits corresponding to the field are added. A carry-in value from less significant bits is concurrently...http://www.google.de/patents/US5970512?utm_source=gb-gplus-sharePatent US5970512 - Translation shadow array adder-decoder circuit for selecting consecutive TLB entries
