A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further...http://www.google.de/patents/US6480059?utm_source=gb-gplus-sharePatent US6480059 - Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances
