A memory cell is provided with a first access transistor coupled to a first terminal of the storage transistor and a second access transistor coupled to a second terminal of the storage transistor is disclosed. The gates of the access transistors are coupled to word lines. In the inactive state, the...http://www.google.de/patents/US20020167834?utm_source=gb-gplus-sharePatent US20020167834 - Memory cell having reduced leakage current
