A method of generating a clock may use an analog synchronous mirror delay (ASMD) circuit with a duty cycle correction scheme, and an internal clock generator may use one or more of the ASMD circuits, The ASMD circuit may include a comparator with first and second input terminals that generates an output...http://www.google.de/patents/US6801067?utm_source=gb-gplus-sharePatent US6801067 - Analog synchronous mirror delay circuit, method of generating a clock and internal clock generator using the same
