A semiconductor memory comprises a memory cell (20) array in which memory cells (M) are placed at the intersections of word lines (WL1 to WLM) and bit lines (BL1 to BLn), a bit line select circuit (21) coupled with the bit lines (BL1 to BLn) for selecting the bit lines, a potential supply circuit (22)...http://www.google.de/patents/US5430678?utm_source=gb-gplus-sharePatent US5430678 - Semiconductor memory having redundant cells
