A signal processor has a single random access memory having a capacity equal to or greater than the total number of words in a processing interval. An address sequence mechanism is operatively connected to the memory for addressing the memory in a sequence for, after the first processing interval, reading...http://www.google.de/patents/US4320466?utm_source=gb-gplus-sharePatent US4320466 - Address sequence mechanism for reordering data continuously over some interval using a single memory structure
