An interface controller coupled between the main memory system and the I/O system of a large data processing system which controller is able to receive memory access requests from a number of different peripheral devices. The memory interface controller is provided with a data array for holding a number...http://www.google.de/patents/US5446844?utm_source=gb-gplus-sharePatent US5446844 - Peripheral memory interface controller as a cache for a large data processing system
