A substantially noise-free data input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates either a logical true or complement output signal representation of a data input signal and includes timing circuitry to delay an edge transition on the output...http://www.google.de/patents/US6294939?utm_source=gb-gplus-sharePatent US6294939 - Device and method for data input buffering
