A method for operating a semiconductor memory device having first and second bit lines, a gate electrode, an insulative layer, and a substrate includes applying first, second, and third biases to the first bit line, the second bit line, and the gate electrode, respectively, to induce carriers from the...http://www.google.de/patents/US7483299?utm_source=gb-gplus-sharePatent US7483299 - Devices and operation methods for reducing second bit effect in memory device
