In a synchronous semiconductor memory device, a predecoder is provided between a former stage address input register formed of first latch circuits and a latter stage address input register formed of second latch circuits. The first and second latch circuits operate in response to first and second internal...http://www.google.de/patents/US6026036?utm_source=gb-gplus-sharePatent US6026036 - Synchronous semiconductor memory device having set up time of external address signal reduced
