Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and...http://www.google.de/patents/US20060237768?utm_source=gb-gplus-sharePatent US20060237768 - Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
