A DRAM capacitor contact comprised of a silicon oxide layer with a trench having sidewalls and a form in the silicon oxide layer. A dielectric liner is coated on the sidewalls of the trench. A metal layer is then deposited between the sidewalls and polished to form a bit-line. One or more dielectric...http://www.google.de/patents/US6262450?utm_source=gb-gplus-sharePatent US6262450 - DRAM stack capacitor with vias and conductive connection extending from above conductive lines to the substrate
